179 lines
4.2 KiB
C
179 lines
4.2 KiB
C
#include "../config.h"
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#include "../makros.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/wdt.h>
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#include "borg_hw.h"
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/*
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// those macros get defined via menuconfig, now
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// 16 columns total directly controlled, therefore 2 ports
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#define COLPORT1 PORTA
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#define COLDDR1 DDRA
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#define COLPORT2 PORTC
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#define COLDDR2 DDRC
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// the other port controls the shift registers
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#define ROWPORT PORTD
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#define ROWDDR DDRD
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// both clock and reset are connected to each shift register
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// reset pin is negated
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#define PIN_MCLR PD4
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#define PIN_CLK PD5
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// these are the individual data input pins for the shift registers
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#define PIN_DATA1 PD6
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#define PIN_DATA2 PD7
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*/
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#define COLDDR1 DDR(COLPORT1)
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#define COLDDR2 DDR(COLPORT2)
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#define ROWDDR DDR(ROWPORT)
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#if defined (__AVR_ATmega644P__) || defined (__AVR_ATmega644__) || (__AVR_ATmega1284P__) || defined (__AVR_ATmega1284__)
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/* more ifdef magic :-( */
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#define OCR0 OCR0A
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#define TIMER0_COMP_vect TIMER0_COMPA_vect
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#endif
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// buffer which holds the currently shown frame
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES];
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// display a row
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static void rowshow(unsigned char row, unsigned char plane) {
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//reset states of preceding row
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COLPORT1 = 0;
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COLPORT2 = 0;
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// short delay loop, to ensure proper deactivation of the drivers
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unsigned char i;
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for (i = 0; i < 20; i++) {
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asm volatile("nop");
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}
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if (row == 0) {
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// row 0: initialize first shift register
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ROWPORT &= ~(1 << PIN_MCLR);
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ROWPORT |= (1 << PIN_MCLR);
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ROWPORT |= (1 << PIN_DATA1);
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ROWPORT |= (1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_DATA1);
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// depending on the currently drawn plane, display the row for a
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// specific amount of time
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static unsigned char const ocr0_table[] = {5, 8, 20};
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OCR0 = ocr0_table[plane];
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} else if (row == 8) {
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// row 8: initialize second shift register
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ROWPORT &= ~(1 << PIN_MCLR);
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ROWPORT |= (1 << PIN_MCLR);
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ROWPORT |= (1 << PIN_DATA2);
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ROWPORT |= (1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_DATA2);
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} else {
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// remaining rows: just shift forward
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ROWPORT |= (1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_CLK);
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}
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// another delay loop, to ensure that the drivers are ready
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for (i = 0; i < 20; i++) {
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asm volatile("nop");
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}
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// output data of the current row to the column drivers
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COLPORT1 = pixmap[plane][row][0];
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COLPORT2 = pixmap[plane][row][1];
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}
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// depending on the plane this interrupt gets triggered at 50 kHz, 31.25 kHz or
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// 12.5 kHz
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ISR(TIMER0_COMP_vect) {
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static unsigned char plane = 0;
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static unsigned char row = 0;
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// reset watchdog
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wdt_reset();
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// output current row according to current plane
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rowshow(row, plane);
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// increment both row and plane
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if (++row == NUM_ROWS) {
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row = 0;
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if (++plane == NUMPLANE) {
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plane = 0;
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}
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}
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}
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void timer0_off() {
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cli();
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COLPORT1 = 0;
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COLPORT2 = 0;
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ROWPORT = 0;
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#if defined (__AVR_ATmega644P__) || defined (__AVR_ATmega644__) || (__AVR_ATmega1284P__) || defined (__AVR_ATmega1284__)
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TCCR0A = 0x00;
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TCCR0B = 0x00;
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#else
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TCCR0 = 0x00;
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#endif
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sei();
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}
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// initialize timer which triggers the interrupt
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static void timer0_on() {
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/* TCCR0: FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00
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CS02 CS01 CS00
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0 0 0 stop
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0 0 1 clk
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0 1 0 clk/8
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0 1 1 clk/64
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1 0 0 clk/256
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1 0 1 clk/1024
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*/
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#if defined (__AVR_ATmega644P__) || defined (__AVR_ATmega644__) || (__AVR_ATmega1284P__) || defined (__AVR_ATmega1284__)
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TCCR0A = 0x02; // CTC Mode
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TCCR0B = 0x03; // clk/64
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TCNT0 = 0; // reset timer
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OCR0 = 20; // compare with this value
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TIMSK0 = 0x02; // compare match Interrupt on
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#else
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TCCR0 = 0x0B; // CTC Mode, clk/64
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TCNT0 = 0; // reset timer
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OCR0 = 20; // compare with this value
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TIMSK = 0x02; // compare match Interrupt on
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#endif
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}
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void borg_hw_init() {
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// switch column ports to output mode
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COLDDR1 = 0xFF;
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COLDDR2 = 0xFF;
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// switch pins of the row port to output mode
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ROWDDR = (1<<PIN_MCLR) | (1<<PIN_CLK) | (1<<PIN_DATA1) | (1<<PIN_DATA2);
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// switch off all columns for now
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COLPORT1 = 0;
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COLPORT2 = 0;
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// reset shift registers for the rows
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ROWPORT = 0;
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timer0_on();
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// activate watchdog timer
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wdt_reset();
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wdt_enable(0x00); // 17ms watchdog
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}
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