First attempt at nrf support code
This commit is contained in:
Stefan `Sec` Zehl
parent
8c0c89e407
commit
a03f202e7c
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@ -105,6 +105,11 @@
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#define RB_HB5 1,2
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#define RB_HB5_IO IOCON_PIO1_2
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// Funk
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#define RB_NRF_CE 1,5
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#define RB_NRF_CE_IO IOCON_PIO1_5
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#define RB_SPI_NRF_CS 1,10
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#define RB_SPI_NRF_CS_IO IOCON_PIO1_10
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// Misc
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#define RB_BUSINT 3,0
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@ -0,0 +1,36 @@
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##########################################################################
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# User configuration and firmware specific object files
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##########################################################################
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OBJS =
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OBJS += nrf24l01p.o
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LIBNAME=funk
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##########################################################################
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# GNU GCC compiler flags
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##########################################################################
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ROOT_PATH?= ..
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INCLUDE_PATHS = -I$(ROOT_PATH) -I../core -I.
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include $(ROOT_PATH)/Makefile.inc
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LIBFILE=lib$(LIBNAME).a
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##########################################################################
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# Compiler settings, parameters and flags
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##########################################################################
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all: $(LIBFILE)
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$(LIBFILE): $(OBJS)
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$(AR) rcs $@ $(OBJS)
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%.o : %.c
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$(CC) $(CFLAGS) -o $@ $<
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clean:
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rm -f $(OBJS) $(LIBFILE)
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nrf24l01p.o: nrf24l01p.h
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@ -0,0 +1,103 @@
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#include <basic/basic.h>
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#include <nrf24l01p.h>
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#include "core/ssp/ssp.h"
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#define CHANNEL_BEACON 81
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#define DEFAULT_SPEED R_RF_SETUP_DR_2M
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#define MAC_BEACON "BEACO"
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/*-----------------------------------------------------------------------*/
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/* Transmit a byte via SPI (Platform dependent) */
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/*-----------------------------------------------------------------------*/
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void xmit_spi(uint8_t dat) {
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sspSend(0, (uint8_t*) &dat, 1);
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}
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/*-----------------------------------------------------------------------*/
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/* Receive a byte from MMC via SPI (Platform dependent) */
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/*-----------------------------------------------------------------------*/
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uint8_t rcvr_spi (void) {
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uint8_t data = 0;
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sspReceive(0, &data, 1);
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return data;
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}
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#define rcvr_spi_m(dst) \
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do { \
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sspReceive(0, (uint8_t*)(dst), 1); \
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} while(0)
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#define CS_LOW() gpioSetValue(RB_SPI_NRF_CS, 0)
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#define CS_HIGH() gpioSetValue(RB_SPI_NRF_CS, 1)
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void nrf_cmd(uint8_t cmd){
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xmit_spi(cmd);
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};
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uint8_t nrf_cmd_status(uint8_t cmd){
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xmit_spi(cmd);
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return rcvr_spi();
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};
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void nrf_write_reg(uint8_t reg, uint8_t val){
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xmit_spi(C_W_REGISTER | reg);
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xmit_spi(val);
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};
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uint8_t nrf_read_reg(uint8_t reg, uint8_t val){
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xmit_spi(C_R_REGISTER | reg);
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// do i need to read the status byte here?
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xmit_spi(val);
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return rcvr_spi();
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};
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void nrf_write_reg_long(uint8_t reg, int len, char* data){
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xmit_spi(C_W_REGISTER | reg);
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for(int i=0;i<len;i++){
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xmit_spi(data[i]);
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};
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};
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void nrf_init() {
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// Enable SPI correctly
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sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
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// Enable CS & CE pins
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gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
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gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
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gpioSetDir(RB_NRF_CE, gpioDirection_Output);
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gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
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// Setup for nrf24l01+
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// power up takes 1.5ms - 3.5ms (depending on crystal)
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nrf_write_reg(R_CONFIG,
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R_CONFIG_PRIM_RX| // Receive mode
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R_CONFIG_PWR_UP| // Power on
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R_CONFIG_CRCO // 2-byte CRC
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);
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nrf_write_reg(R_EN_AA, 0); // Disable Enhanced ShockBurst;
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nrf_write_reg(R_RF_CH, CHANNEL_BEACON &127); // Select channel
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// enable receive pipes
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nrf_write_reg(R_EN_RXADDR,R_EN_RXADDR_ERX_P0
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// |R_EN_RXADDR_ERX_P1
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);
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nrf_write_reg(R_RX_PW_P0,16);
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nrf_write_reg_long(R_RX_ADDR_P0,5,"\x1\x2\x3\x2\1");
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// nrf_write_reg(R_RX_PW_P1,16);
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// nrf_write_reg_long(R_RX_ADDR_P1,5,"R0KET");
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// OpenBeacon transmit address
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nrf_write_reg_long(R_TX_ADDR,5,MAC_BEACON);
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// Set speed / strength
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nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|R_RF_SETUP_RF_PWR_3);
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// XXX: or write R_CONFIG last?
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};
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@ -0,0 +1,96 @@
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#ifndef _NRF24L01P_H
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#define _NRF24L01P_H 1
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// SPI commands
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#define C_R_REGISTER 0x00
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#define C_W_REGISTER 0x20
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#define C_R_RX_PAYLOAD 0x61
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#define C_W_TX_PAYLOAD 0xA0
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#define C_FLUSH_TX 0xE1
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#define C_FLUSH_RX 0xE2
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#define C_REUSE_TX_PL 0xE3
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#define C_R_RX_PL_WID 0x60
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#define C_W_ACK_PAYLOAD 0xA8
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#define C_W_TX_PAYLOAD_NOCACK 0xB0
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#define C_NOP 0xFF
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// Registers
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#define R_CONFIG 0x00
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#define R_EN_AA 0x01
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#define R_EN_RXADDR 0x02
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#define R_SETUP_AW 0x03
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#define R_SETUP_RETR 0x04
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#define R_RF_CH 0x05
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#define R_RF_SETUP 0x06
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#define R_STATUS 0x07
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#define R_OBSERVE_TX 0x08
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#define R_RPD 0x09
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#define R_RX_ADDR_P0 0x0A
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#define R_RX_ADDR_P0_LEN 5
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#define R_RX_ADDR_P1 0x0B
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#define R_RX_ADDR_P1_LEN 5
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#define R_RX_ADDR_P2 0x0C
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#define R_RX_ADDR_P2_LEN 1
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#define R_RX_ADDR_P3 0x0D
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#define R_RX_ADDR_P3_LEN 1
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#define R_RX_ADDR_P4 0x0E
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#define R_RX_ADDR_P4_LEN 1
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#define R_RX_ADDR_P5 0x0F
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#define R_RX_ADDR_P5_LEN 1
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#define R_TX_ADDR 0x10
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#define R_TX_ADDR_LEN 5
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#define R_RX_PW_P0 0x11
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#define R_RX_PW_P1 0x12
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#define R_RX_PW_P2 0x13
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#define R_RX_PW_P3 0x14
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#define R_RX_PW_P4 0x15
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#define R_RX_PW_P5 0x16
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#define R_FIFO_STATUS 0x17
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#define R_DYNPD 0x1c
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// Register Flags
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//CONFIG register definitions
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#define R_CONFIG_RESERVED 0x80
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#define R_CONFIG_MASK_RX_DR 0x40
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#define R_CONFIG_MASK_TX_DS 0x20
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#define R_CONFIG_MASK_MAX_RT 0x10
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#define R_CONFIG_EN_CRC 0x08
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#define R_CONFIG_CRCO 0x04
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#define R_CONFIG_PWR_UP 0x02
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#define R_CONFIG_PRIM_RX 0x01
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//EN_AA register definitions
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#define R_EN_AA_ENAA_P5 0x20
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#define R_EN_AA_ENAA_P4 0x10
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#define R_EN_AA_ENAA_P3 0x08
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#define R_EN_AA_ENAA_P2 0x04
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#define R_EN_AA_ENAA_P1 0x02
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#define R_EN_AA_ENAA_P0 0x01
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#define R_EN_AA_ENAA_NONE 0x00
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//EN_RXADDR register definitions
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#define R_EN_RXADDR_ERX_P5 0x20
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#define R_EN_RXADDR_ERX_P4 0x10
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#define R_EN_RXADDR_ERX_P3 0x08
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#define R_EN_RXADDR_ERX_P2 0x04
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#define R_EN_RXADDR_ERX_P1 0x02
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#define R_EN_RXADDR_ERX_P0 0x01
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#define R_EN_RXADDR_ERX_NONE 0x00
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//RF_SETUP register definitions
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#define R_RF_CONT_WAVE 0x80
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#define R_RF_SETUP_RF_DR_LOW 0x20
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#define R_RF_SETUP_PLL_LOCK 0x10
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#define R_RF_SETUP_RF_DR_HIGH 0x08
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#define R_RF_SETUP_RF_PWR_0 0x00
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#define R_RF_SETUP_RF_PWR_1 0x02
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#define R_RF_SETUP_RF_PWR_2 0x04
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#define R_RF_SETUP_RF_PWR_3 0x06
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#define R_RF_SETUP_DR_1M 0x00
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#define R_RF_SETUP_DR_2M 0x08
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#define R_RF_SETUP_DR_250K 0x20
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#endif /* _NRF24L01P_H */
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