From 3e571e7892921c2d481efe2de37bff9ff66bb87b Mon Sep 17 00:00:00 2001 From: Fisch Date: Sun, 6 Oct 2019 12:51:05 +0200 Subject: [PATCH] add opamp powerdistribution board --- .../powerdistribution.kicad_pcb | 898 ++++++++++++++++++ .../powerdistribution/powerdistribution.pro | 33 + .../powerdistribution/powerdistribution.sch | 542 +++++++++++ 3 files changed, 1473 insertions(+) create mode 100644 schematic/powerdistribution/powerdistribution.kicad_pcb create mode 100644 schematic/powerdistribution/powerdistribution.pro create mode 100644 schematic/powerdistribution/powerdistribution.sch diff --git a/schematic/powerdistribution/powerdistribution.kicad_pcb b/schematic/powerdistribution/powerdistribution.kicad_pcb new file mode 100644 index 0000000..da70778 --- /dev/null +++ b/schematic/powerdistribution/powerdistribution.kicad_pcb @@ -0,0 +1,898 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.0.2-bee76a0~70~ubuntu16.04.1) + + (general + (thickness 1.6) + (drawings 40) + (tracks 116) + (zones 0) + (modules 20) + (nets 4) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 2) + (trace_clearance 0.2) + (zone_clearance 2) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 2) + (via_drill 0.8) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 6 1.5) + (pad_drill 0) + (pad_to_mask_clearance 0.051) + (solder_mask_min_width 0.25) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GNDA) + (net 2 -15V) + (net 3 +15V) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 2) + (via_dia 2) + (via_drill 0.8) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +15V) + (add_net -15V) + (add_net GNDA) + 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2142 50 0000 L CNN +F 1 "Opamp_power_out-gnd" H 7100 2100 50 0000 L CNN +F 2 "footprints:edge_solderstrip_1mm5x6mm" H 6750 2100 50 0001 C CNN +F 3 "~" H 6750 2100 50 0001 C CNN + 1 6750 2100 + 1 0 0 -1 +$EndComp +$Comp +L Connector_Generic:Conn_01x01 JoutP6 +U 1 1 5D99C8EB +P 6750 2200 +F 0 "JoutP6" H 6829 2242 50 0000 L CNN +F 1 "Opamp_power_out+15" H 7100 2200 50 0000 L CNN +F 2 "footprints:edge_solderstrip_1mm5x6mm" H 6750 2200 50 0001 C CNN +F 3 "~" H 6750 2200 50 0001 C CNN + 1 6750 2200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC