diff --git a/01_Matlab/01_Libraries/01_Controller/BLDC_controller_Lib.slx b/01_Matlab/01_Libraries/01_Controller/BLDC_controller_Lib.slx index 0cda7ff..545ac3c 100644 Binary files a/01_Matlab/01_Libraries/01_Controller/BLDC_controller_Lib.slx and b/01_Matlab/01_Libraries/01_Controller/BLDC_controller_Lib.slx differ diff --git a/01_Matlab/03_CreateParamTable/tableParamType.xlsx b/01_Matlab/03_CreateParamTable/tableParamType.xlsx index 521bc8c..919cbbe 100644 Binary files a/01_Matlab/03_CreateParamTable/tableParamType.xlsx and b/01_Matlab/03_CreateParamTable/tableParamType.xlsx differ diff --git a/01_Matlab/BLDCmotorControl_FOC_R2017b_fixdt.slx b/01_Matlab/BLDCmotorControl_FOC_R2017b_fixdt.slx index df23a69..efcee1b 100644 Binary files a/01_Matlab/BLDCmotorControl_FOC_R2017b_fixdt.slx and b/01_Matlab/BLDCmotorControl_FOC_R2017b_fixdt.slx differ diff --git a/01_Matlab/init_model.m b/01_Matlab/init_model.m index 2e45e9c..5f14239 100644 --- a/01_Matlab/init_model.m +++ b/01_Matlab/init_model.m @@ -95,7 +95,7 @@ r_errInpTgtThres = 200; % [-] Error input target threshold (for "Blo % Current measurement b_selPhaABCurrMeas = 1; % [-] Measured phase currents selection: {iA,iB} = 1 (default); {iB,iC} = 0 -dV_openRate = 1000 * Ts_ctrl; % [V/s] Rate for voltage cut-off in Open Mode (Sample Time included in the rate) +dV_openRate = 1000 / f_ctrl; % [V/s] Rate for voltage cut-off in Open Mode (Sample Time included in the rate) % Field Weakening b_fieldWeakEna = 0; % [-] Field weakening enable flag: 0 = disable (default), 1 = enable @@ -109,18 +109,15 @@ r_fieldWeak_XA = [570 600 630 660 690 720 750 780 810 840 870 90 % Q axis control gains cf_iqKp = 0.5; % [-] P gain -cf_iqKi = 100 * Ts_ctrl; % [-] I gain -cf_iqKb = 1000 * Ts_ctrl; % [-] Back calculation gain for integral anti-windup +cf_iqKi = 100 / f_ctrl; % [-] I gain % D axis control gains cf_idKp = 0.2; % [-] P gain -cf_idKi = 60 * Ts_ctrl; % [-] I gain -cf_idKb = 1000 * Ts_ctrl; % [-] Back calculation gain for integral anti-windup +cf_idKi = 60 / f_ctrl; % [-] I gain % Speed control gains cf_nKp = 1.18; % [-] P gain -cf_nKi = 20.4 * Ts_ctrl; % [-] I gain -cf_nKb = 1000 * Ts_ctrl; % [-] Back calculation gain for integral anti-windup +cf_nKi = 20.4 / f_ctrl; % [-] I gain % Limitations %------------------------------- @@ -138,7 +135,7 @@ n_max = 800; % [rpm] Maximum motor speed % Current Limitations cf_iqKpLimProt = 7.2; % [-] Current limit protection gain (only used in VLT_MODE and SPD_MODE) -cf_iqKiLimProt = 40.7 * Ts_ctrl; % [-] Current limit protection integral gain (only used in SPD_MODE) +cf_iqKiLimProt = 40.7 / f_ctrl; % [-] Current limit protection integral gain (only used in SPD_MODE) i_max = 15; % [A] Maximum allowed motor current (continuous) i_max = i_max * i_sca; iq_max_XA = 0:15:i_max; diff --git a/Inc/BLDC_controller.h b/Inc/BLDC_controller.h index eb1a9e2..350bcd1 100644 --- a/Inc/BLDC_controller.h +++ b/Inc/BLDC_controller.h @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1187 + * Model version : 1.1197 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 27 17:31:20 2019 + * C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -35,27 +35,22 @@ typedef struct { int16_T UnitDelay_DSTATE; /* '/UnitDelay' */ } DW_Counter; +/* Block signals and states (auto storage) for system '/PI_clamp_fixdt_id' */ +typedef struct { + int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ + boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ +} DW_PI_clamp_fixdt; + /* Block signals and states (auto storage) for system '/Low_Pass_Filter' */ typedef struct { int16_T UnitDelay3_DSTATE[2]; /* '/UnitDelay3' */ } DW_Low_Pass_Filter; -/* Block signals and states (auto storage) for system '/PI_backCalc_fixdt_Id' */ +/* Block signals and states (auto storage) for system '/PI_clamp_fixdt_n' */ typedef struct { - int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ - int32_T UnitDelay_DSTATE_l; /* '/UnitDelay' */ -} DW_PI_backCalc_fixdt; - -/* Block signals and states (auto storage) for system '/PI_backCalc_fixdt_n' */ -typedef struct { - int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ - int32_T UnitDelay_DSTATE_h; /* '/UnitDelay' */ -} DW_PI_backCalc_fixdt_f; - -/* Block signals and states (auto storage) for system '/Rate_Limiter' */ -typedef struct { - int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ -} DW_Rate_Limiter; + int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ + boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ +} DW_PI_clamp_fixdt_c; /* Block signals and states (auto storage) for system '/Counter' */ typedef struct { @@ -79,19 +74,19 @@ typedef struct { typedef struct { DW_either_edge either_edge_a; /* '/either_edge' */ DW_Debounce_Filter Debounce_Filter_f;/* '/Debounce_Filter' */ - DW_Rate_Limiter Rate_Limiter_l; /* '/Rate_Limiter' */ - DW_PI_backCalc_fixdt PI_backCalc_fixdt_Iq;/* '/PI_backCalc_fixdt_Iq' */ - DW_PI_backCalc_fixdt_f PI_backCalc_fixdt_n_p;/* '/PI_backCalc_fixdt_n' */ - DW_PI_backCalc_fixdt PI_backCalc_fixdt_Id;/* '/PI_backCalc_fixdt_Id' */ + DW_PI_clamp_fixdt PI_clamp_fixdt_iq; /* '/PI_clamp_fixdt_iq' */ + DW_PI_clamp_fixdt_c PI_clamp_fixdt_n_o;/* '/PI_clamp_fixdt_n' */ DW_Low_Pass_Filter Low_Pass_Filter_m;/* '/Low_Pass_Filter' */ + DW_PI_clamp_fixdt PI_clamp_fixdt_id; /* '/PI_clamp_fixdt_id' */ DW_Counter Counter_e; /* '/Counter' */ + int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ int16_T Gain4[3]; /* '/Gain4' */ int16_T Sum1[2]; /* '/Sum1' */ int16_T z_counterRawPrev; /* '/z_counterRawPrev' */ int16_T Merge; /* '/Merge' */ int16_T Divide1; /* '/Divide1' */ int16_T Divide4; /* '/Divide4' */ - int16_T Switch2; /* '/Switch2' */ + int16_T Switch1; /* '/Switch1' */ int16_T Divide11; /* '/Divide11' */ int16_T UnitDelay3_DSTATE; /* '/UnitDelay3' */ int16_T UnitDelay4_DSTATE; /* '/UnitDelay4' */ @@ -101,22 +96,23 @@ typedef struct { int16_T UnitDelay5_DSTATE; /* '/UnitDelay5' */ int16_T UnitDelay4_DSTATE_e; /* '/UnitDelay4' */ int16_T UnitDelay4_DSTATE_er; /* '/UnitDelay4' */ - int8_T Switch2_e; /* '/Switch2' */ + int8_T Switch2; /* '/Switch2' */ int8_T UnitDelay2_DSTATE_b; /* '/UnitDelay2' */ int8_T If2_ActiveSubsystem; /* '/If2' */ int8_T If1_ActiveSubsystem; /* '/If1' */ - int8_T If1_ActiveSubsystem_h; /* '/If1' */ + int8_T If2_ActiveSubsystem_a; /* '/If2' */ + int8_T If1_ActiveSubsystem_e; /* '/If1' */ int8_T If1_ActiveSubsystem_f; /* '/If1' */ int8_T If2_ActiveSubsystem_c; /* '/If2' */ int8_T SwitchCase_ActiveSubsystem; /* '/Switch Case' */ - uint8_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ uint8_T UnitDelay3_DSTATE_fy; /* '/UnitDelay3' */ - uint8_T UnitDelay1_DSTATE_m; /* '/UnitDelay1' */ + uint8_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ uint8_T UnitDelay2_DSTATE_f; /* '/UnitDelay2' */ - uint8_T UnitDelay_DSTATE; /* '/UnitDelay' */ - uint8_T is_active_c1_BLDC_controller;/* '/F02_02_Control_Mode_Manager' */ - uint8_T is_c1_BLDC_controller; /* '/F02_02_Control_Mode_Manager' */ - uint8_T is_ACTIVE; /* '/F02_02_Control_Mode_Manager' */ + uint8_T UnitDelay1_DSTATE_p; /* '/UnitDelay1' */ + uint8_T UnitDelay_DSTATE_c; /* '/UnitDelay' */ + uint8_T is_active_c1_BLDC_controller;/* '/F03_02_Control_Mode_Manager' */ + uint8_T is_c1_BLDC_controller; /* '/F03_02_Control_Mode_Manager' */ + uint8_T is_ACTIVE; /* '/F03_02_Control_Mode_Manager' */ boolean_T Merge_n; /* '/Merge' */ boolean_T dz_cntTrnsDet; /* '/dz_cntTrnsDet' */ boolean_T UnitDelay_DSTATE_g; /* '/UnitDelay' */ @@ -206,7 +202,7 @@ struct P_ { * Referenced by: '/t_errQual' */ uint16_T cf_idKp; /* Variable: cf_idKp - * Referenced by: '/cf_idKp' + * Referenced by: '/cf_idKp1' */ uint16_T cf_iqKp; /* Variable: cf_iqKp * Referenced by: '/cf_iqKp' @@ -265,14 +261,8 @@ struct P_ { uint16_T cf_currFilt; /* Variable: cf_currFilt * Referenced by: '/cf_currFilt' */ - uint16_T cf_idKb; /* Variable: cf_idKb - * Referenced by: '/cf_idKb' - */ uint16_T cf_idKi; /* Variable: cf_idKi - * Referenced by: '/cf_idKi' - */ - uint16_T cf_iqKb; /* Variable: cf_iqKb - * Referenced by: '/cf_iqKb' + * Referenced by: '/cf_idKi1' */ uint16_T cf_iqKi; /* Variable: cf_iqKi * Referenced by: '/cf_iqKi' @@ -280,9 +270,6 @@ struct P_ { uint16_T cf_iqKiLimProt; /* Variable: cf_iqKiLimProt * Referenced by: '/cf_iqKiLimProt' */ - uint16_T cf_nKb; /* Variable: cf_nKb - * Referenced by: '/cf_nKb' - */ uint16_T cf_nKi; /* Variable: cf_nKi * Referenced by: '/cf_nKi' */ @@ -338,20 +325,12 @@ extern void BLDC_controller_step(RT_MODEL *const rtM); * Block '/Scope12' : Unused code path elimination * Block '/Scope8' : Unused code path elimination * Block '/Scope9' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination * Block '/Data Type Duplicate' : Unused code path elimination * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination * Block '/Data Type Conversion2' : Eliminate redundant data type conversion * Block '/Data Type Conversion3' : Eliminate redundant data type conversion * Block '/Data Type Conversion6' : Eliminate redundant data type conversion @@ -402,8 +381,8 @@ extern void BLDC_controller_step(RT_MODEL *const rtM); * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Dequalification/Counter/rst_Delay' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Qualification/Counter' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Qualification/Counter/rst_Delay' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F02_01_Mode_Transition_Calculation' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F02_02_Control_Mode_Manager' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_01_Mode_Transition_Calculation' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_02_Control_Mode_Manager' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Clarke_Transform' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Current_Filtering' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Field_Weakening' @@ -427,19 +406,21 @@ extern void BLDC_controller_step(RT_MODEL *const rtM); * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Open_Mode/rising_edge_init' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Open_Mode/Rate_Limiter/Delay_Init1' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Open_Mode/Rate_Limiter/Saturation Dynamic' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_backCalc_fixdt_n' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/Saturation Dynamic1' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_backCalc_fixdt_n/Integrator' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_backCalc_fixdt_n/Saturation Dynamic1' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_backCalc_fixdt_Iq' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_clamp_fixdt_n' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_clamp_fixdt_n/Clamping_circuit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_clamp_fixdt_n/Integrator' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Speed_Mode/PI_clamp_fixdt_n/Saturation_hit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_clamp_fixdt_iq' * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/Saturation Dynamic' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_backCalc_fixdt_Iq/Integrator' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_backCalc_fixdt_Iq/Saturation Dynamic1' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_backCalc_fixdt_Id' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/Saturation Dynamic' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_backCalc_fixdt_Id/Integrator' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_backCalc_fixdt_Id/Saturation Dynamic1' - * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Voltage_Mode/Saturation Dynamic1' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_clamp_fixdt_iq/Clamping_circuit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_clamp_fixdt_iq/Integrator' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Torque_Mode/PI_clamp_fixdt_iq/Saturation_hit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_clamp_fixdt_id' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/Saturation Dynamic' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_clamp_fixdt_id/Clamping_circuit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_clamp_fixdt_id/Integrator' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Vd_Calculation/PI_clamp_fixdt_id/Saturation_hit' + * '' : 'BLDCmotorControl_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Oriented_Control/Voltage_Mode/Saturation Dynamic1' */ #endif /* RTW_HEADER_BLDC_controller_h_ */ diff --git a/Inc/config.h b/Inc/config.h index 73b1df2..afb6c79 100644 --- a/Inc/config.h +++ b/Inc/config.h @@ -7,7 +7,7 @@ #define DEAD_TIME 32 // PWM deadtime #define DELAY_IN_MAIN_LOOP 5 // in ms. default 5. it is independent of all the timing critical stuff. do not touch if you do not know what you are doing. #define TIMEOUT 5 // number of wrong / missing input commands before emergency off -#define A2BIT_CONV 50 // bits per A on ADC. Example: 50 = 1 A, 100 = 2 A, etc +#define A2BIT_CONV 50 // A to bit for current conversion on ADC. Example: 1 A = 50, 2 A = 100, etc // ADC conversion time definitions #define ADC_CONV_TIME_1C5 (14) //Total ADC clock cycles / conversion = ( 1.5+12.5) @@ -127,9 +127,9 @@ #define CTRL_MOD_REQ 1 // [-] Control mode request: 0 = Open mode, 1 = Voltage mode (default), 2 = Speed mode, 3 = Torque mode #define DIAG_ENA 1 // [-] Motor Diagnostics enable flag: 0 = Disabled, 1 = Enabled (default) #define FIELD_WEAK_ENA 0 // [-] Field Weakening enable flag: 0 = Disabled (default), 1 = Enabled -#define I_MOT_MAX (15 * A2BIT_CONV) << 4 // [A] Maximum motor current limit (Change only the first number, the rest is needed for fixed-point conversion) +#define I_MOT_MAX (15 * A2BIT_CONV) << 4 // [A] Maximum motor current limit (Change only the first number, the rest is needed for fixed-point conversion, fixdt(1,16,4)) #define I_DC_MAX (17 * A2BIT_CONV) // [A] Maximum DC Link current limit (This is the final current protection. Above this value, current chopping is applied. To avoid this make sure that I_DC_MAX = I_MOT_MAX + 2A ) -#define N_MOT_MAX 800 << 4 // [rpm] Maximum motor speed (change only the first number, the rest is needed for fixed-point conversion) +#define N_MOT_MAX 800 << 4 // [rpm] Maximum motor speed (change only the first number, the rest is needed for fixed-point conversion, fixdt(1,16,4)) /* GENERAL NOTES: @@ -164,10 +164,10 @@ #define FILTER 6553 // 0.1f [-] lower value == softer filter [0, 65535] = [0.0 - 1.0]. // Value of COEFFICIENT is in fixdt(1,16,14) -// If VAL_floatingPoint >= 0, VAL_fixedPoint = VAL_floatingPoint * 2^15 -// If VAL_floatingPoint < 0, VAL_fixedPoint = 2^16 + floor(VAL_floatingPoint * 2^15). +// If VAL_floatingPoint >= 0, VAL_fixedPoint = VAL_floatingPoint * 2^14 +// If VAL_floatingPoint < 0, VAL_fixedPoint = 2^16 + floor(VAL_floatingPoint * 2^14). #define SPEED_COEFFICIENT 16384 // 1.0f [-] higher value == stronger. [0, 65535] = [-2.0 - 2.0]. In this case 16384 = 1.0 * 2^14 -#define STEER_COEFFICIENT 8192 // 0.5f [-] higher value == stronger. [0, 65535] = [-2.0 - 2.0]. In this case 8192 = 0.5 * 2^15. If you do not want any steering, set it to 0. +#define STEER_COEFFICIENT 8192 // 0.5f [-] higher value == stronger. [0, 65535] = [-2.0 - 2.0]. In this case 8192 = 0.5 * 2^14. If you do not want any steering, set it to 0. #define INVERT_R_DIRECTION #define INVERT_L_DIRECTION diff --git a/Inc/rtwtypes.h b/Inc/rtwtypes.h index ac495a5..2ffd35b 100644 --- a/Inc/rtwtypes.h +++ b/Inc/rtwtypes.h @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1187 + * Model version : 1.1197 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 27 17:31:20 2019 + * C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex diff --git a/Src/BLDC_controller.c b/Src/BLDC_controller.c index 69e267f..ce21dcd 100644 --- a/Src/BLDC_controller.c +++ b/Src/BLDC_controller.c @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1187 + * Model version : 1.1197 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 27 17:31:20 2019 + * C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -19,7 +19,7 @@ #include "BLDC_controller.h" -/* Named constants for Chart: '/F02_02_Control_Mode_Manager' */ +/* Named constants for Chart: '/F03_02_Control_Mode_Manager' */ #define IN_ACTIVE ((uint8_T)1U) #define IN_NO_ACTIVE_CHILD ((uint8_T)0U) #define IN_OPEN ((uint8_T)2U) @@ -104,20 +104,17 @@ int16_T intrp1d_s16s32s32u8u8n6l_s(uint8_T bpIndex, uint8_T frac, const int16_T extern void Counter_Init(DW_Counter *localDW, int16_T rtp_z_cntInit); extern int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter *localDW); +extern void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW); +extern void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T + *rty_out, DW_PI_clamp_fixdt *localDW); extern void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW); extern void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2], DW_Low_Pass_Filter *localDW); -extern void PI_backCalc_fixdt_Reset(DW_PI_backCalc_fixdt *localDW); -extern void PI_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - uint16_T rtu_Kb, int32_T rtu_ext_limProt, int16_T rtu_satMax, int16_T - rtu_satMin, int16_T *rty_out, DW_PI_backCalc_fixdt *localDW); -extern void PI_backCalc_fixdt_n_Reset(DW_PI_backCalc_fixdt_f *localDW); -extern int16_T PI_backCalc_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T - rtu_I, uint16_T rtu_Kb, int16_T rtu_ext_limProt, int16_T rtu_satMax, int16_T - rtu_satMin, DW_PI_backCalc_fixdt_f *localDW); -extern void Rate_Limiter_Reset(DW_Rate_Limiter *localDW); -extern int32_T Rate_Limiter(int32_T rtu_u, int32_T rtu_initVal, boolean_T - rtu_init, int32_T rtu_inc, int32_T rtu_dec, DW_Rate_Limiter *localDW); +extern void PI_clamp_fixdt_n_Reset(DW_PI_clamp_fixdt_c *localDW); +extern int16_T PI_clamp_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt, + DW_PI_clamp_fixdt_c *localDW); extern void Counter_b_Init(DW_Counter_l *localDW, uint16_T rtp_z_cntInit); extern uint16_T Counter_i(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, DW_Counter_l *localDW); @@ -273,6 +270,149 @@ int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter return rty_cnt_0; } +/* + * System reset for atomic system: + * '/PI_clamp_fixdt_id' + * '/PI_clamp_fixdt_iq' + */ +void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + localDW->UnitDelay1_DSTATE = false; + + /* InitializeConditions for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE = 0; +} + +/* + * Output and update for atomic system: + * '/PI_clamp_fixdt_id' + * '/PI_clamp_fixdt_iq' + */ +void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T + rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, + int16_T *rty_out, DW_PI_clamp_fixdt *localDW) +{ + boolean_T rtb_LowerRelop1_e; + boolean_T rtb_UpperRelop_f; + int32_T rtb_Sum1_b4; + int32_T q0; + int32_T tmp; + int16_T tmp_0; + + /* Sum: '/Sum2' incorporates: + * Product: '/Divide2' + */ + q0 = rtu_err * rtu_I; + if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { + q0 = MIN_int32_T; + } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { + q0 = MAX_int32_T; + } else { + q0 += rtu_ext_limProt; + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/a_elecPeriod1' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' + */ + if (localDW->UnitDelay1_DSTATE) { + tmp = 0; + } else { + tmp = q0; + } + + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' incorporates: + * UnitDelay: '/UnitDelay' + */ + rtb_Sum1_b4 = tmp + localDW->UnitDelay_DSTATE; + + /* Product: '/Divide5' */ + tmp = (rtu_err * rtu_P) >> 11; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* Sum: '/Sum1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Product: '/Divide5' + */ + tmp = (((rtb_Sum1_b4 >> 16) << 1) + tmp) >> 1; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* RelationalOperator: '/LowerRelop1' incorporates: + * Sum: '/Sum1' + */ + rtb_LowerRelop1_e = ((int16_T)tmp > rtu_satMax); + + /* RelationalOperator: '/UpperRelop' incorporates: + * Sum: '/Sum1' + */ + rtb_UpperRelop_f = ((int16_T)tmp < rtu_satMin); + + /* Switch: '/Switch1' incorporates: + * Sum: '/Sum1' + * Switch: '/Switch3' + */ + if (rtb_LowerRelop1_e) { + *rty_out = rtu_satMax; + } else if (rtb_UpperRelop_f) { + /* Switch: '/Switch3' */ + *rty_out = rtu_satMin; + } else { + *rty_out = (int16_T)tmp; + } + + /* End of Switch: '/Switch1' */ + + /* Signum: '/SignDeltaU2' incorporates: + * Sum: '/Sum2' + */ + if (q0 < 0) { + q0 = -1; + } else { + q0 = (q0 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Signum: '/SignDeltaU3' incorporates: + * Sum: '/Sum1' + */ + if ((int16_T)tmp < 0) { + tmp_0 = -1; + } else { + tmp_0 = (int16_T)((int16_T)tmp > 0); + } + + /* End of Signum: '/SignDeltaU3' */ + + /* Update for UnitDelay: '/UnitDelay1' incorporates: + * DataTypeConversion: '/DataTypeConv4' + * Logic: '/AND1' + * Logic: '/AND1' + * RelationalOperator: '/Equal1' + */ + localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_e || + rtb_UpperRelop_f)); + + /* Update for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE = rtb_Sum1_b4; +} + /* System reset for atomic system: '/Low_Pass_Filter' */ void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW) { @@ -313,165 +453,61 @@ void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2] localDW->UnitDelay3_DSTATE[1] = rty_y[1]; } -/* - * System reset for atomic system: - * '/PI_backCalc_fixdt_Id' - * '/PI_backCalc_fixdt_Iq' - */ -void PI_backCalc_fixdt_Reset(DW_PI_backCalc_fixdt *localDW) +/* System reset for atomic system: '/PI_clamp_fixdt_n' */ +void PI_clamp_fixdt_n_Reset(DW_PI_clamp_fixdt_c *localDW) { - /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = 0; - - /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_l = 0; -} - -/* - * Output and update for atomic system: - * '/PI_backCalc_fixdt_Id' - * '/PI_backCalc_fixdt_Iq' - */ -void PI_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, uint16_T - rtu_Kb, int32_T rtu_ext_limProt, int16_T rtu_satMax, int16_T rtu_satMin, - int16_T *rty_out, DW_PI_backCalc_fixdt *localDW) -{ - int32_T rtb_Sum1_i4; - int32_T tmp; - - /* Sum: '/Sum2' incorporates: - * Product: '/Divide1' - * UnitDelay: '/UnitDelay' - */ - rtb_Sum1_i4 = rtu_err * rtu_I; - if ((rtb_Sum1_i4 < 0) && (rtu_ext_limProt < MIN_int32_T - rtb_Sum1_i4)) { - rtb_Sum1_i4 = MIN_int32_T; - } else if ((rtb_Sum1_i4 > 0) && (rtu_ext_limProt > MAX_int32_T - rtb_Sum1_i4)) - { - rtb_Sum1_i4 = MAX_int32_T; - } else { - rtb_Sum1_i4 += rtu_ext_limProt; - } - - if ((rtb_Sum1_i4 < 0) && (localDW->UnitDelay_DSTATE < MIN_int32_T - - rtb_Sum1_i4)) { - rtb_Sum1_i4 = MIN_int32_T; - } else if ((rtb_Sum1_i4 > 0) && (localDW->UnitDelay_DSTATE > MAX_int32_T - - rtb_Sum1_i4)) { - rtb_Sum1_i4 = MAX_int32_T; - } else { - rtb_Sum1_i4 += localDW->UnitDelay_DSTATE; - } - - /* End of Sum: '/Sum2' */ - - /* Sum: '/Sum1' incorporates: - * UnitDelay: '/UnitDelay' - */ - rtb_Sum1_i4 += localDW->UnitDelay_DSTATE_l; - - /* Product: '/Divide4' */ - tmp = (rtu_err * rtu_P) >> 11; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* Sum: '/Sum6' incorporates: - * DataTypeConversion: '/Data Type Conversion1' - * Product: '/Divide4' - */ - tmp = (((rtb_Sum1_i4 >> 16) << 1) + tmp) >> 1; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Sum: '/Sum6' - * Switch: '/Switch' - */ - if ((int16_T)tmp > rtu_satMax) { - *rty_out = rtu_satMax; - } else if ((int16_T)tmp < rtu_satMin) { - /* Switch: '/Switch' */ - *rty_out = rtu_satMin; - } else { - *rty_out = (int16_T)tmp; - } - - /* End of Switch: '/Switch2' */ - - /* Update for UnitDelay: '/UnitDelay' incorporates: - * Product: '/Divide2' - * Sum: '/Sum3' - * Sum: '/Sum6' - */ - localDW->UnitDelay_DSTATE = (int16_T)(*rty_out - (int16_T)tmp) * rtu_Kb; - - /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_l = rtb_Sum1_i4; -} - -/* System reset for atomic system: '/PI_backCalc_fixdt_n' */ -void PI_backCalc_fixdt_n_Reset(DW_PI_backCalc_fixdt_f *localDW) -{ - /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = 0; + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + localDW->UnitDelay1_DSTATE = false; /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_h = 0; + localDW->UnitDelay_DSTATE = 0; } -/* Output and update for atomic system: '/PI_backCalc_fixdt_n' */ -int16_T PI_backCalc_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - uint16_T rtu_Kb, int16_T rtu_ext_limProt, int16_T rtu_satMax, int16_T - rtu_satMin, DW_PI_backCalc_fixdt_f *localDW) +/* Output and update for atomic system: '/PI_clamp_fixdt_n' */ +int16_T PI_clamp_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int16_T rtu_satMax, int16_T rtu_satMin, int16_T rtu_ext_limProt, + DW_PI_clamp_fixdt_c *localDW) { - int32_T rtb_Sum1_l; + boolean_T rtb_LowerRelop1_ge; + boolean_T rtb_UpperRelop_cm; + int32_T rtb_Sum1_mz; + int32_T q0; int32_T q1; + int16_T tmp; int16_T rty_out_0; /* Sum: '/Sum2' incorporates: - * Product: '/Divide1' - * UnitDelay: '/UnitDelay' + * Product: '/Divide2' */ - rtb_Sum1_l = rtu_err * rtu_I; + q0 = rtu_err * rtu_I; q1 = rtu_ext_limProt << 10; - if ((rtb_Sum1_l < 0) && (q1 < MIN_int32_T - rtb_Sum1_l)) { - rtb_Sum1_l = MIN_int32_T; - } else if ((rtb_Sum1_l > 0) && (q1 > MAX_int32_T - rtb_Sum1_l)) { - rtb_Sum1_l = MAX_int32_T; + if ((q0 < 0) && (q1 < MIN_int32_T - q0)) { + q0 = MIN_int32_T; + } else if ((q0 > 0) && (q1 > MAX_int32_T - q0)) { + q0 = MAX_int32_T; } else { - rtb_Sum1_l += q1; + q0 += q1; } - if ((rtb_Sum1_l < 0) && (localDW->UnitDelay_DSTATE < MIN_int32_T - rtb_Sum1_l)) - { - rtb_Sum1_l = MIN_int32_T; - } else if ((rtb_Sum1_l > 0) && (localDW->UnitDelay_DSTATE > MAX_int32_T - - rtb_Sum1_l)) { - rtb_Sum1_l = MAX_int32_T; + /* Switch: '/Switch1' incorporates: + * Constant: '/a_elecPeriod1' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' + */ + if (localDW->UnitDelay1_DSTATE) { + q1 = 0; } else { - rtb_Sum1_l += localDW->UnitDelay_DSTATE; + q1 = q0; } - /* End of Sum: '/Sum2' */ + /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' incorporates: * UnitDelay: '/UnitDelay' */ - rtb_Sum1_l += localDW->UnitDelay_DSTATE_h; + rtb_Sum1_mz = q1 + localDW->UnitDelay_DSTATE; - /* Product: '/Divide4' */ + /* Product: '/Divide5' */ q1 = (rtu_err * rtu_P) >> 11; if (q1 > 32767) { q1 = 32767; @@ -481,11 +517,11 @@ int16_T PI_backCalc_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, } } - /* Sum: '/Sum6' incorporates: + /* Sum: '/Sum1' incorporates: * DataTypeConversion: '/Data Type Conversion1' - * Product: '/Divide4' + * Product: '/Divide5' */ - q1 = (((rtb_Sum1_l >> 16) << 1) + q1) >> 1; + q1 = (((rtb_Sum1_mz >> 16) << 1) + q1) >> 1; if (q1 > 32767) { q1 = 32767; } else { @@ -494,100 +530,67 @@ int16_T PI_backCalc_fixdt_n(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, } } - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Sum: '/Sum6' - * Switch: '/Switch' + /* RelationalOperator: '/LowerRelop1' incorporates: + * Sum: '/Sum1' */ - if ((int16_T)q1 > rtu_satMax) { + rtb_LowerRelop1_ge = ((int16_T)q1 > rtu_satMax); + + /* RelationalOperator: '/UpperRelop' incorporates: + * Sum: '/Sum1' + */ + rtb_UpperRelop_cm = ((int16_T)q1 < rtu_satMin); + + /* Switch: '/Switch1' incorporates: + * Sum: '/Sum1' + * Switch: '/Switch3' + */ + if (rtb_LowerRelop1_ge) { rty_out_0 = rtu_satMax; - } else if ((int16_T)q1 < rtu_satMin) { - /* Switch: '/Switch' */ + } else if (rtb_UpperRelop_cm) { + /* Switch: '/Switch3' */ rty_out_0 = rtu_satMin; } else { rty_out_0 = (int16_T)q1; } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch1' */ - /* Update for UnitDelay: '/UnitDelay' incorporates: - * Product: '/Divide2' - * Sum: '/Sum3' - * Sum: '/Sum6' + /* Signum: '/SignDeltaU2' incorporates: + * Sum: '/Sum2' */ - localDW->UnitDelay_DSTATE = (int16_T)(rty_out_0 - (int16_T)q1) * rtu_Kb; + if (q0 < 0) { + q0 = -1; + } else { + q0 = (q0 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Signum: '/SignDeltaU3' incorporates: + * Sum: '/Sum1' + */ + if ((int16_T)q1 < 0) { + tmp = -1; + } else { + tmp = (int16_T)((int16_T)q1 > 0); + } + + /* End of Signum: '/SignDeltaU3' */ + + /* Update for UnitDelay: '/UnitDelay1' incorporates: + * DataTypeConversion: '/DataTypeConv4' + * Logic: '/AND1' + * Logic: '/AND1' + * RelationalOperator: '/Equal1' + */ + localDW->UnitDelay1_DSTATE = ((q0 == tmp) && (rtb_LowerRelop1_ge || + rtb_UpperRelop_cm)); /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_h = rtb_Sum1_l; + localDW->UnitDelay_DSTATE = rtb_Sum1_mz; return rty_out_0; } -/* System reset for atomic system: '/Rate_Limiter' */ -void Rate_Limiter_Reset(DW_Rate_Limiter *localDW) -{ - /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = 0; -} - -/* Output and update for atomic system: '/Rate_Limiter' */ -int32_T Rate_Limiter(int32_T rtu_u, int32_T rtu_initVal, boolean_T rtu_init, - int32_T rtu_inc, int32_T rtu_dec, DW_Rate_Limiter *localDW) -{ - int32_T rtb_Switch1_h; - int32_T rtb_Sum1_k; - int32_T rty_y_0; - - /* Switch: '/Switch1' incorporates: - * UnitDelay: '/UnitDelay' - */ - if (rtu_init) { - rtb_Switch1_h = rtu_initVal; - } else { - rtb_Switch1_h = localDW->UnitDelay_DSTATE; - } - - /* End of Switch: '/Switch1' */ - - /* Sum: '/Sum1' */ - rtb_Sum1_k = rtu_u - rtb_Switch1_h; - rtb_Sum1_k = (rtb_Sum1_k & 134217728) != 0 ? rtb_Sum1_k | -134217728 : - rtb_Sum1_k & 134217727; - - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_Sum1_k > rtu_inc) { - rtb_Sum1_k = rtu_inc; - } else { - if (rtb_Sum1_k < rtu_dec) { - /* Switch: '/Switch' */ - rtb_Sum1_k = rtu_dec; - } - } - - /* End of Switch: '/Switch2' */ - - /* Sum: '/Sum2' */ - rtb_Sum1_k += rtb_Switch1_h; - rty_y_0 = (rtb_Sum1_k & 134217728) != 0 ? rtb_Sum1_k | -134217728 : rtb_Sum1_k - & 134217727; - - /* Switch: '/Switch2' */ - if (rtu_init) { - /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = rtu_initVal; - } else { - /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = rty_y_0; - } - - /* End of Switch: '/Switch2' */ - return rty_y_0; -} - /* * System initialize for atomic system: * '/Counter' @@ -782,35 +785,33 @@ void BLDC_controller_step(RT_MODEL *const rtM) DW *rtDW = ((DW *) rtM->dwork); ExtU *rtU = (ExtU *) rtM->inputs; ExtY *rtY = (ExtY *) rtM->outputs; - int32_T tmp; uint8_T rtb_Sum; boolean_T rtb_LogicalOperator; int8_T rtb_Sum2_h; boolean_T rtb_RelationalOperator4_d; boolean_T rtb_RelationalOperator1_m; uint8_T rtb_Sum_l; - uint8_T rtb_iq_max_XA; - int16_T rtb_Saturation2; + uint8_T rtb_r_fieldWeak_XA_o1; int16_T rtb_Merge; int16_T rtb_Switch2_fv; int16_T rtb_Abs5; - int16_T rtb_Switch1_a; + int16_T rtb_Switch1_l; int16_T rtb_Switch2_d; uint16_T rtb_Divide2_h; int16_T rtb_Saturation; - int16_T rtb_Sum6; - int16_T rtb_Add; - int16_T rtb_TmpSignalConversionAtLow_Pa[2]; + int16_T rtb_toNegative; + int16_T rtb_Gain4; uint8_T rtb_r_fieldWeak_XA_o2; - int16_T rtb_Gain1; - int16_T rtb_Gain6; - int32_T rtb_Sum2; - int16_T tmp_0[4]; + int16_T rtb_Gain2_f; + int16_T rtb_id_fieldWeak_M1; + int16_T rtb_MinMax2; + int16_T rtb_TmpSignalConversionAtLow_Pa[2]; + int32_T rtb_DataTypeConversion; + int32_T rtb_Switch1; + int32_T rtb_Sum1; + int32_T rtb_Gain3; + int16_T tmp[4]; int8_T UnitDelay3; - int32_T tmp_1; - int32_T tmp_2; - int32_T tmp_3; - int16_T rtb_Switch2_d_0; /* Outputs for Atomic SubSystem: '/BLDC_controller' */ /* Sum: '/Sum' incorporates: @@ -826,29 +827,15 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Saturate: '/Saturation2' incorporates: * Inport: '/r_inpTgt' */ - tmp = rtU->r_inpTgt << 4; - if (tmp >= 16000) { - rtb_Saturation2 = 16000; - } else if (tmp <= -16000) { - rtb_Saturation2 = -16000; - } else { - rtb_Saturation2 = (int16_T)(rtU->r_inpTgt << 4); - } - - /* End of Saturate: '/Saturation2' */ + rtb_Gain3 = rtU->r_inpTgt << 4; /* If: '/If1' incorporates: * Constant: '/z_ctrlTypSel1' + * Inport: '/r_inpTgt' * Inport: '/r_inpTgt' + * Saturate: '/Saturation2' */ - if (rtP->z_ctrlTypSel == 0) { - /* Outputs for IfAction SubSystem: '/Commutation_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - rtb_Merge = rtb_Saturation2; - - /* End of Outputs for SubSystem: '/Commutation_Control_Type' */ - } else { + if (rtP->z_ctrlTypSel == 1) { /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: * ActionPort: '/Action Port' */ @@ -858,20 +845,63 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Constant: '/i_max' * Constant: '/n_max' */ - tmp_0[0] = 0; - tmp_0[1] = rtP->Vd_max; - tmp_0[2] = rtP->n_max; - tmp_0[3] = rtP->i_max; - - /* Product: '/Divide1' incorporates: - * Product: '/Divide4' - * Selector: '/Selector' - * UnitDelay: '/UnitDelay1' - */ - rtb_Merge = (int16_T)(((uint16_T)((tmp_0[rtDW->UnitDelay1_DSTATE] << 5) / - 125) * rtb_Saturation2) >> 12); + tmp[0] = 0; + tmp[1] = rtP->Vd_max; + tmp[2] = rtP->n_max; + tmp[3] = rtP->i_max; /* End of Outputs for SubSystem: '/FOC_Control_Type' */ + + /* Saturate: '/Saturation2' incorporates: + * Inport: '/r_inpTgt' + */ + if (rtb_Gain3 >= 16000) { + rtb_Gain4 = 16000; + } else if (rtb_Gain3 <= -16000) { + rtb_Gain4 = -16000; + } else { + rtb_Gain4 = (int16_T)(rtU->r_inpTgt << 4); + } + + /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Product: '/Divide1' incorporates: + * Inport: '/z_ctrlModReq' + * Product: '/Divide4' + * Selector: '/Selector' + */ + rtb_Merge = (int16_T)(((uint16_T)((tmp[rtU->z_ctrlModReq] << 5) / 125) * + rtb_Gain4) >> 12); + + /* End of Outputs for SubSystem: '/FOC_Control_Type' */ + } else if (rtb_Gain3 >= 16000) { + /* Outputs for IfAction SubSystem: '/Commutation_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation2' incorporates: + * Inport: '/r_inpTgt' + */ + rtb_Merge = 16000; + + /* End of Outputs for SubSystem: '/Commutation_Control_Type' */ + } else if (rtb_Gain3 <= -16000) { + /* Outputs for IfAction SubSystem: '/Commutation_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation2' incorporates: + * Inport: '/r_inpTgt' + */ + rtb_Merge = -16000; + + /* End of Outputs for SubSystem: '/Commutation_Control_Type' */ + } else { + /* Outputs for IfAction SubSystem: '/Commutation_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + rtb_Merge = (int16_T)(rtU->r_inpTgt << 4); + + /* End of Outputs for SubSystem: '/Commutation_Control_Type' */ } /* End of If: '/If1' */ @@ -886,7 +916,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) */ rtb_LogicalOperator = (boolean_T)((rtU->b_hallA != 0) ^ (rtU->b_hallB != 0) ^ (rtU->b_hallC != 0) ^ (rtDW->UnitDelay3_DSTATE_fy != 0) ^ - (rtDW->UnitDelay1_DSTATE_m != 0)) ^ (rtDW->UnitDelay2_DSTATE_f != 0); + (rtDW->UnitDelay1_DSTATE != 0)) ^ (rtDW->UnitDelay2_DSTATE_f != 0); /* If: '/If2' incorporates: * If: '/If2' @@ -898,7 +928,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ /* UnitDelay: '/UnitDelay3' */ - UnitDelay3 = rtDW->Switch2_e; + UnitDelay3 = rtDW->Switch2; /* Sum: '/Sum2' incorporates: * Constant: '/vec_hallToPos' @@ -918,9 +948,9 @@ void BLDC_controller_step(RT_MODEL *const rtM) * RelationalOperator: '/Relational Operator6' */ if ((rtb_Sum2_h == 1) || (rtb_Sum2_h == -5)) { - rtDW->Switch2_e = 1; + rtDW->Switch2 = 1; } else { - rtDW->Switch2_e = -1; + rtDW->Switch2 = -1; } /* End of Switch: '/Switch2' */ @@ -948,18 +978,18 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Abs: '/Abs2' */ if (rtb_Switch2_fv < 0) { - rtb_Switch1_a = (int16_T)-rtb_Switch2_fv; + rtb_Switch1_l = (int16_T)-rtb_Switch2_fv; } else { - rtb_Switch1_a = rtb_Switch2_fv; + rtb_Switch1_l = rtb_Switch2_fv; } /* End of Abs: '/Abs2' */ /* Relay: '/dz_cntTrnsDet' */ - if (rtb_Switch1_a >= rtP->dz_cntTrnsDetHi) { + if (rtb_Switch1_l >= rtP->dz_cntTrnsDetHi) { rtDW->dz_cntTrnsDet_Mode = true; } else { - if (rtb_Switch1_a <= rtP->dz_cntTrnsDetLo) { + if (rtb_Switch1_l <= rtP->dz_cntTrnsDetLo) { rtDW->dz_cntTrnsDet_Mode = false; } } @@ -969,7 +999,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of Relay: '/dz_cntTrnsDet' */ /* RelationalOperator: '/Relational Operator4' */ - rtb_RelationalOperator4_d = (rtDW->Switch2_e != UnitDelay3); + rtb_RelationalOperator4_d = (rtDW->Switch2 != UnitDelay3); /* Switch: '/Switch3' incorporates: * Constant: '/Constant4' @@ -979,19 +1009,19 @@ void BLDC_controller_step(RT_MODEL *const rtM) * UnitDelay: '/UnitDelay1' */ if (rtb_RelationalOperator4_d && rtDW->UnitDelay1_DSTATE_n) { - rtb_Switch1_a = 0; + rtb_Switch1_l = 0; } else if (rtb_RelationalOperator4_d) { /* Switch: '/Switch2' incorporates: * UnitDelay: '/UnitDelay4' */ - rtb_Switch1_a = rtDW->UnitDelay4_DSTATE_e; + rtb_Switch1_l = rtDW->UnitDelay4_DSTATE_e; } else if (rtDW->dz_cntTrnsDet) { /* Switch: '/Switch1' incorporates: * Constant: '/cf_speedCoef' * Product: '/Divide14' * Switch: '/Switch2' */ - rtb_Switch1_a = (int16_T)((rtP->cf_speedCoef << 4) / + rtb_Switch1_l = (int16_T)((rtP->cf_speedCoef << 4) / rtDW->z_counterRawPrev); } else { /* Switch: '/Switch1' incorporates: @@ -1004,7 +1034,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) * UnitDelay: '/UnitDelay3' * UnitDelay: '/UnitDelay5' */ - rtb_Switch1_a = (int16_T)(((uint16_T)(rtP->cf_speedCoef << 2) << 4) / + rtb_Switch1_l = (int16_T)(((uint16_T)(rtP->cf_speedCoef << 2) << 4) / (int16_T)(((rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE_o) + rtDW->UnitDelay5_DSTATE) + rtDW->z_counterRawPrev)); } @@ -1012,7 +1042,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of Switch: '/Switch3' */ /* Product: '/Divide11' */ - rtDW->Divide11 = (int16_T)(rtb_Switch1_a * rtDW->Switch2_e); + rtDW->Divide11 = (int16_T)(rtb_Switch1_l * rtDW->Switch2); /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE_p = rtDW->z_counterRawPrev; @@ -1043,7 +1073,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Constant: '/Constant6' incorporates: * Constant: '/z_maxCntRst2' */ - rtb_Switch1_a = (int16_T) Counter(1, rtP->z_maxCntRst, rtb_LogicalOperator, + rtb_Switch1_l = (int16_T) Counter(1, rtP->z_maxCntRst, rtb_LogicalOperator, &rtDW->Counter_e); /* End of Outputs for SubSystem: '/Counter' */ @@ -1053,7 +1083,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Constant: '/z_maxCntRst' * RelationalOperator: '/Relational Operator2' */ - if (rtb_Switch1_a > rtP->z_maxCntRst) { + if (rtb_Switch1_l > rtP->z_maxCntRst) { rtb_Switch2_fv = 0; } else { rtb_Switch2_fv = rtDW->Divide11; @@ -1086,7 +1116,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) * RelationalOperator: '/Relational Operator3' * Relay: '/n_commDeacv' */ - rtb_LogicalOperator = ((rtP->z_ctrlTypSel != 0) && rtDW->n_commDeacv_Mode && ( + rtb_LogicalOperator = ((rtP->z_ctrlTypSel == 1) && rtDW->n_commDeacv_Mode && ( !rtDW->dz_cntTrnsDet)); /* RelationalOperator: '/Relational Operator9' incorporates: @@ -1126,7 +1156,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* InitializeConditions for If: '/If2' incorporates: * UnitDelay: '/UnitDelay' */ - rtDW->UnitDelay_DSTATE = 0U; + rtDW->UnitDelay_DSTATE_c = 0U; /* End of InitializeConditions for SubSystem: '/F02_Diagnostics' */ @@ -1162,22 +1192,22 @@ void BLDC_controller_step(RT_MODEL *const rtM) * UnitDelay: '/UnitDelay' * UnitDelay: '/UnitDelay4' */ - if ((rtDW->UnitDelay_DSTATE & 4) != 0) { + if ((rtDW->UnitDelay_DSTATE_c & 4) != 0) { rtb_RelationalOperator1_m = true; } else { if (rtDW->UnitDelay4_DSTATE < 0) { /* Abs: '/Abs4' incorporates: * UnitDelay: '/UnitDelay4' */ - rtb_Switch2_d_0 = (int16_T)-rtDW->UnitDelay4_DSTATE; + rtb_Gain4 = (int16_T)-rtDW->UnitDelay4_DSTATE; } else { /* Abs: '/Abs4' incorporates: * UnitDelay: '/UnitDelay4' */ - rtb_Switch2_d_0 = rtDW->UnitDelay4_DSTATE; + rtb_Gain4 = rtDW->UnitDelay4_DSTATE; } - rtb_RelationalOperator1_m = ((rtb_Switch2_d_0 > rtP->r_errInpTgtThres) && + rtb_RelationalOperator1_m = ((rtb_Gain4 > rtP->r_errInpTgtThres) && rtb_RelationalOperator4_d); } @@ -1219,7 +1249,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Outport: '/z_errCode' incorporates: * UnitDelay: '/UnitDelay' */ - rtY->z_errCode = rtDW->UnitDelay_DSTATE; + rtY->z_errCode = rtDW->UnitDelay_DSTATE_c; } /* End of Switch: '/Switch1' */ @@ -1227,7 +1257,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Update for UnitDelay: '/UnitDelay' incorporates: * Outport: '/z_errCode' */ - rtDW->UnitDelay_DSTATE = rtY->z_errCode; + rtDW->UnitDelay_DSTATE_c = rtY->z_errCode; /* End of Outputs for SubSystem: '/F02_Diagnostics' */ } @@ -1247,10 +1277,10 @@ void BLDC_controller_step(RT_MODEL *const rtM) * UnitDelay: '/UnitDelay1' */ rtb_RelationalOperator1_m = ((!rtU->b_motEna) || rtDW->Merge_n || - (rtU->z_ctrlModReq == 0) || ((rtU->z_ctrlModReq != rtDW->UnitDelay1_DSTATE) && - (rtDW->UnitDelay1_DSTATE != 0))); + (rtU->z_ctrlModReq == 0) || ((rtU->z_ctrlModReq != rtDW->UnitDelay1_DSTATE_p) + && (rtDW->UnitDelay1_DSTATE_p != 0))); - /* Chart: '/F02_02_Control_Mode_Manager' incorporates: + /* Chart: '/F03_02_Control_Mode_Manager' incorporates: * Constant: '/constant' * Constant: '/constant1' * Constant: '/constant5' @@ -1309,7 +1339,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* End of Chart: '/F02_02_Control_Mode_Manager' */ + /* End of Chart: '/F03_02_Control_Mode_Manager' */ /* Switch: '/Switch2' incorporates: * Constant: '/Constant16' @@ -1321,7 +1351,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) */ if (rtb_LogicalOperator) { /* MinMax: '/MinMax' */ - rtb_Switch2_d = rtb_Switch1_a; + rtb_Switch2_d = rtb_Switch1_l; if (!(rtb_Switch2_d < rtDW->z_counterRawPrev)) { rtb_Switch2_d = rtDW->z_counterRawPrev; } @@ -1335,16 +1365,16 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Selector: '/Selector' * Sum: '/Sum1' */ - if (rtDW->Switch2_e == 1) { + if (rtDW->Switch2 == 1) { rtb_Sum2_h = rtConstP.vec_hallToPos_Value[rtb_Sum]; } else { rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Sum] + 1); } rtb_Switch2_d = (int16_T)(((int16_T)((int16_T)((rtb_Switch2_d << 14) / - rtDW->z_counterRawPrev) * rtDW->Switch2_e) + (rtb_Sum2_h << 14)) >> 2); + rtDW->z_counterRawPrev) * rtDW->Switch2) + (rtb_Sum2_h << 14)) >> 2); } else { - if (rtDW->Switch2_e == 1) { + if (rtDW->Switch2 == 1) { /* Switch: '/Switch3' incorporates: * Constant: '/vec_hallToPos' * Selector: '/Selector' @@ -1379,10 +1409,10 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Saturate: '/Saturation' incorporates: * Inport: '/i_phaAB' */ - tmp = rtU->i_phaAB << 4; - if (tmp >= 32000) { + rtb_Gain3 = rtU->i_phaAB << 4; + if (rtb_Gain3 >= 32000) { rtb_Saturation = 32000; - } else if (tmp <= -32000) { + } else if (rtb_Gain3 <= -32000) { rtb_Saturation = -32000; } else { rtb_Saturation = (int16_T)(rtU->i_phaAB << 4); @@ -1393,10 +1423,10 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Saturate: '/Saturation1' incorporates: * Inport: '/i_phaBC' */ - tmp = rtU->i_phaBC << 4; - if (tmp >= 32000) { + rtb_Gain3 = rtU->i_phaBC << 4; + if (rtb_Gain3 >= 32000) { rtb_Switch2_d = 32000; - } else if (tmp <= -32000) { + } else if (rtb_Gain3 <= -32000) { rtb_Switch2_d = -32000; } else { rtb_Switch2_d = (int16_T)(rtU->i_phaBC << 4); @@ -1406,23 +1436,35 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* If: '/If1' incorporates: * Constant: '/z_ctrlTypSel1' - * Constant: '/cf_currFilt' */ rtb_Sum2_h = rtDW->If1_ActiveSubsystem; UnitDelay3 = -1; - if (rtP->z_ctrlTypSel != 0) { + if (rtP->z_ctrlTypSel == 1) { UnitDelay3 = 0; } rtDW->If1_ActiveSubsystem = UnitDelay3; if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { - /* Disable for If: '/If1' */ - if (rtDW->If1_ActiveSubsystem_h == 0) { - /* Disable for Outport: '/Vd' */ - rtDW->Switch2 = 0; + /* Disable for If: '/If2' */ + if (rtDW->If2_ActiveSubsystem_a == 0) { + /* Disable for Outport: '/iq' */ + rtDW->Sum1[0] = 0; + + /* Disable for Outport: '/id' */ + rtDW->Sum1[1] = 0; } - rtDW->If1_ActiveSubsystem_h = -1; + rtDW->If2_ActiveSubsystem_a = -1; + + /* End of Disable for If: '/If2' */ + + /* Disable for If: '/If1' */ + if (rtDW->If1_ActiveSubsystem_e == 0) { + /* Disable for Outport: '/Vd' */ + rtDW->Switch1 = 0; + } + + rtDW->If1_ActiveSubsystem_e = -1; /* End of Disable for If: '/If1' */ @@ -1479,154 +1521,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->UnitDelay4_DSTATE_er = 0; /* End of InitializeConditions for SubSystem: '/F04_Field_Oriented_Control' */ - - /* SystemReset for IfAction SubSystem: '/F04_Field_Oriented_Control' incorporates: - * ActionPort: '/Action Port' - */ - - /* SystemReset for Atomic SubSystem: '/Low_Pass_Filter' */ - - /* SystemReset for If: '/If1' */ - Low_Pass_Filter_Reset(&rtDW->Low_Pass_Filter_m); - - /* End of SystemReset for SubSystem: '/Low_Pass_Filter' */ - - /* End of SystemReset for SubSystem: '/F04_Field_Oriented_Control' */ } /* Outputs for IfAction SubSystem: '/F04_Field_Oriented_Control' incorporates: * ActionPort: '/Action Port' */ - /* If: '/If1' incorporates: - * Constant: '/b_selPhaABCurrMeas' - */ - if (rtP->b_selPhaABCurrMeas) { - /* Outputs for IfAction SubSystem: '/Clarke_PhasesAB' incorporates: - * ActionPort: '/Action Port' - */ - /* Gain: '/Gain4' */ - tmp = 18919 * rtb_Saturation; - - /* Gain: '/Gain2' */ - tmp_3 = 18919 * rtb_Switch2_d; - - /* Sum: '/Sum1' incorporates: - * Gain: '/Gain2' - * Gain: '/Gain4' - */ - tmp = (((tmp < 0 ? 32767 : 0) + tmp) >> 15) + (int16_T)(((tmp_3 < 0 ? - 16383 : 0) + tmp_3) >> 14); - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - rtb_Sum6 = (int16_T)tmp; - - /* End of Sum: '/Sum1' */ - /* End of Outputs for SubSystem: '/Clarke_PhasesAB' */ - } else { - /* Outputs for IfAction SubSystem: '/Clarke_PhasesBC' incorporates: - * ActionPort: '/Action Port' - */ - /* Sum: '/Sum3' */ - tmp = rtb_Saturation - rtb_Switch2_d; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* Gain: '/Gain2' incorporates: - * Sum: '/Sum3' - */ - tmp *= 18919; - rtb_Sum6 = (int16_T)(((tmp < 0 ? 32767 : 0) + tmp) >> 15); - - /* Sum: '/Sum1' */ - tmp = -rtb_Saturation - rtb_Switch2_d; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - rtb_Saturation = (int16_T)tmp; - - /* End of Sum: '/Sum1' */ - /* End of Outputs for SubSystem: '/Clarke_PhasesBC' */ - } - - /* End of If: '/If1' */ - - /* PreLookup: '/a_elecAngle_XA' */ - rtb_iq_max_XA = plook_u8u16_evencka(rtb_Divide2_h, 0U, 128U, 180U); - - /* Interpolation_n-D: '/r_sin_M1' */ - rtb_Add = rtConstP.r_sin_M1_Table[rtb_iq_max_XA]; - - /* Interpolation_n-D: '/r_cos_M1' */ - rtb_Switch2_d = rtConstP.r_cos_M1_Table[rtb_iq_max_XA]; - - /* Sum: '/Sum6' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide1' - * Product: '/Divide4' - */ - tmp = (int16_T)((rtb_Sum6 * rtConstP.r_cos_M1_Table[rtb_iq_max_XA]) >> 14) - - (int16_T)((rtb_Saturation * rtConstP.r_sin_M1_Table[rtb_iq_max_XA]) >> 14); - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: - * Sum: '/Sum6' - */ - rtb_TmpSignalConversionAtLow_Pa[0] = (int16_T)tmp; - - /* Sum: '/Sum1' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide2' - * Product: '/Divide3' - */ - tmp = (int16_T)((rtb_Saturation * rtConstP.r_cos_M1_Table[rtb_iq_max_XA]) >> - 14) + (int16_T)((rtb_Sum6 * - rtConstP.r_sin_M1_Table[rtb_iq_max_XA]) >> 14); - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: - * Sum: '/Sum1' - */ - rtb_TmpSignalConversionAtLow_Pa[1] = (int16_T)tmp; - - /* Outputs for Atomic SubSystem: '/Low_Pass_Filter' */ - Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pa, rtP->cf_currFilt, - rtDW->Sum1, &rtDW->Low_Pass_Filter_m); - - /* End of Outputs for SubSystem: '/Low_Pass_Filter' */ - - /* Relay: '/n_fieldWeakAuth' incorporates: - * Constant: '/cf_currFilt' - */ + /* Relay: '/n_fieldWeakAuth' */ if (rtb_Abs5 >= rtP->n_fieldWeakAuthHi) { rtDW->n_fieldWeakAuth_Mode = true; } else { @@ -1643,53 +1543,231 @@ void BLDC_controller_step(RT_MODEL *const rtM) */ if (rtP->b_fieldWeakEna && rtDW->n_fieldWeakAuth_Mode) { /* Abs: '/Abs5' */ - if (rtb_Saturation2 < 0) { - rtb_Saturation2 = (int16_T)-rtb_Saturation2; + if (rtb_Merge < 0) { + rtb_id_fieldWeak_M1 = (int16_T)-rtb_Merge; + } else { + rtb_id_fieldWeak_M1 = rtb_Merge; } /* End of Abs: '/Abs5' */ /* PreLookup: '/r_fieldWeak_XA' */ - rtb_iq_max_XA = plook_u8s16u8n6_evenc_s(rtb_Saturation2, + rtb_r_fieldWeak_XA_o1 = plook_u8s16u8n6_evenc_s(rtb_id_fieldWeak_M1, rtP->r_fieldWeak_XA[0], (uint16_T)(rtP->r_fieldWeak_XA[1] - rtP->r_fieldWeak_XA[0]), 11U, &rtb_r_fieldWeak_XA_o2); /* Interpolation_n-D: '/id_fieldWeak_M1' */ - rtb_Saturation = intrp1d_s16s32s32u8u8n6l_s(rtb_iq_max_XA, + rtb_id_fieldWeak_M1 = intrp1d_s16s32s32u8u8n6l_s(rtb_r_fieldWeak_XA_o1, rtb_r_fieldWeak_XA_o2, rtP->id_fieldWeak_M1); } else { - rtb_Saturation = 0; + rtb_id_fieldWeak_M1 = 0; } /* End of Switch: '/Switch1' */ /* Gain: '/toNegative' */ - rtb_Saturation2 = (int16_T)-rtb_Saturation; + rtb_toNegative = (int16_T)-rtb_id_fieldWeak_M1; /* Gain: '/Gain4' incorporates: * Constant: '/i_max' */ - rtb_Sum6 = (int16_T)-rtP->i_max; + rtb_Gain4 = (int16_T)-rtP->i_max; + + /* If: '/If1' incorporates: + * Constant: '/b_selPhaABCurrMeas' + */ + if (rtP->b_selPhaABCurrMeas) { + /* Outputs for IfAction SubSystem: '/Clarke_PhasesAB' incorporates: + * ActionPort: '/Action Port' + */ + /* Gain: '/Gain4' */ + rtb_Gain3 = 18919 * rtb_Saturation; + + /* Gain: '/Gain2' */ + rtb_DataTypeConversion = 18919 * rtb_Switch2_d; + + /* Sum: '/Sum1' incorporates: + * Gain: '/Gain2' + * Gain: '/Gain4' + */ + rtb_Gain3 = (((rtb_Gain3 < 0 ? 32767 : 0) + rtb_Gain3) >> 15) + (int16_T) + (((rtb_DataTypeConversion < 0 ? 16383 : 0) + rtb_DataTypeConversion) >> + 14); + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + rtb_Gain2_f = (int16_T)rtb_Gain3; + + /* End of Sum: '/Sum1' */ + /* End of Outputs for SubSystem: '/Clarke_PhasesAB' */ + } else { + /* Outputs for IfAction SubSystem: '/Clarke_PhasesBC' incorporates: + * ActionPort: '/Action Port' + */ + /* Sum: '/Sum3' */ + rtb_Gain3 = rtb_Saturation - rtb_Switch2_d; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* Gain: '/Gain2' incorporates: + * Sum: '/Sum3' + */ + rtb_Gain3 *= 18919; + rtb_Gain2_f = (int16_T)(((rtb_Gain3 < 0 ? 32767 : 0) + rtb_Gain3) >> 15); + + /* Sum: '/Sum1' */ + rtb_Gain3 = -rtb_Saturation - rtb_Switch2_d; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + rtb_Saturation = (int16_T)rtb_Gain3; + + /* End of Sum: '/Sum1' */ + /* End of Outputs for SubSystem: '/Clarke_PhasesBC' */ + } + + /* End of If: '/If1' */ + + /* PreLookup: '/a_elecAngle_XA' */ + rtb_r_fieldWeak_XA_o1 = plook_u8u16_evencka(rtb_Divide2_h, 0U, 128U, 180U); + + /* Interpolation_n-D: '/r_sin_M1' */ + rtb_MinMax2 = rtConstP.r_sin_M1_Table[rtb_r_fieldWeak_XA_o1]; + + /* Interpolation_n-D: '/r_cos_M1' */ + rtb_Switch2_d = rtConstP.r_cos_M1_Table[rtb_r_fieldWeak_XA_o1]; + + /* If: '/If2' incorporates: + * Constant: '/cf_currFilt' + * Inport: '/b_motEna' + */ + rtb_Sum2_h = rtDW->If2_ActiveSubsystem_a; + UnitDelay3 = -1; + if (rtU->b_motEna) { + UnitDelay3 = 0; + } + + rtDW->If2_ActiveSubsystem_a = UnitDelay3; + if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { + /* Disable for Outport: '/iq' */ + rtDW->Sum1[0] = 0; + + /* Disable for Outport: '/id' */ + rtDW->Sum1[1] = 0; + } + + if (UnitDelay3 == 0) { + if (0 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' + */ + + /* SystemReset for Atomic SubSystem: '/Low_Pass_Filter' */ + + /* SystemReset for If: '/If2' */ + Low_Pass_Filter_Reset(&rtDW->Low_Pass_Filter_m); + + /* End of SystemReset for SubSystem: '/Low_Pass_Filter' */ + + /* End of SystemReset for SubSystem: '/Current_Filtering' */ + } + + /* Sum: '/Sum6' incorporates: + * Interpolation_n-D: '/r_cos_M1' + * Interpolation_n-D: '/r_sin_M1' + * Product: '/Divide1' + * Product: '/Divide4' + */ + rtb_Gain3 = (int16_T)((rtb_Gain2_f * + rtConstP.r_cos_M1_Table[rtb_r_fieldWeak_XA_o1]) >> 14) - (int16_T) + ((rtb_Saturation * rtConstP.r_sin_M1_Table[rtb_r_fieldWeak_XA_o1]) >> 14); + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: + * Sum: '/Sum6' + */ + rtb_TmpSignalConversionAtLow_Pa[0] = (int16_T)rtb_Gain3; + + /* End of Outputs for SubSystem: '/Current_Filtering' */ + + /* Sum: '/Sum1' incorporates: + * Interpolation_n-D: '/r_cos_M1' + * Interpolation_n-D: '/r_sin_M1' + * Product: '/Divide2' + * Product: '/Divide3' + */ + rtb_Gain3 = (int16_T)((rtb_Saturation * + rtConstP.r_cos_M1_Table[rtb_r_fieldWeak_XA_o1]) >> 14) + (int16_T) + ((rtb_Gain2_f * rtConstP.r_sin_M1_Table[rtb_r_fieldWeak_XA_o1]) >> 14); + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: + * Sum: '/Sum1' + */ + rtb_TmpSignalConversionAtLow_Pa[1] = (int16_T)rtb_Gain3; + + /* Outputs for Atomic SubSystem: '/Low_Pass_Filter' */ + Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pa, rtP->cf_currFilt, + rtDW->Sum1, &rtDW->Low_Pass_Filter_m); + + /* End of Outputs for SubSystem: '/Low_Pass_Filter' */ + + /* End of Outputs for SubSystem: '/Current_Filtering' */ + } + + /* End of If: '/If2' */ /* If: '/If1' incorporates: * Constant: '/Vd_max1' - * Constant: '/cf_idKb' - * Constant: '/cf_idKi' - * Constant: '/cf_idKp' - * Constant: '/constant' + * Constant: '/cf_idKi1' + * Constant: '/cf_idKp1' + * Constant: '/constant1' * Gain: '/Gain3' * Sum: '/Sum3' */ - rtb_Sum2_h = rtDW->If1_ActiveSubsystem_h; + rtb_Sum2_h = rtDW->If1_ActiveSubsystem_e; UnitDelay3 = -1; if (rtb_LogicalOperator) { UnitDelay3 = 0; } - rtDW->If1_ActiveSubsystem_h = UnitDelay3; + rtDW->If1_ActiveSubsystem_e = UnitDelay3; if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { /* Disable for Outport: '/Vd' */ - rtDW->Switch2 = 0; + rtDW->Switch1 = 0; } if (UnitDelay3 == 0) { @@ -1698,12 +1776,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ - /* SystemReset for Atomic SubSystem: '/PI_backCalc_fixdt_Id' */ + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt_id' */ /* SystemReset for If: '/If1' */ - PI_backCalc_fixdt_Reset(&rtDW->PI_backCalc_fixdt_Id); + PI_clamp_fixdt_Reset(&rtDW->PI_clamp_fixdt_id); - /* End of SystemReset for SubSystem: '/PI_backCalc_fixdt_Id' */ + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt_id' */ /* End of SystemReset for SubSystem: '/Vd_Calculation' */ } @@ -1711,39 +1789,39 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Outputs for IfAction SubSystem: '/Vd_Calculation' incorporates: * ActionPort: '/Action Port' */ - /* Switch: '/Switch2' incorporates: + /* Switch: '/Switch2' incorporates: * Constant: '/i_max' - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' */ - if (rtb_Saturation2 > rtP->i_max) { - rtb_Saturation2 = rtP->i_max; + if (rtb_toNegative > rtP->i_max) { + rtb_toNegative = rtP->i_max; } else { - if (rtb_Saturation2 < rtb_Sum6) { - /* Switch: '/Switch' */ - rtb_Saturation2 = rtb_Sum6; + if (rtb_toNegative < rtb_Gain4) { + /* Switch: '/Switch' */ + rtb_toNegative = rtb_Gain4; } } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch2' */ /* Sum: '/Sum3' */ - tmp = rtb_Saturation2 - rtDW->Sum1[1]; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = rtb_toNegative - rtDW->Sum1[1]; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - /* Outputs for Atomic SubSystem: '/PI_backCalc_fixdt_Id' */ - PI_backCalc_fixdt((int16_T)tmp, rtP->cf_idKp, rtP->cf_idKi, rtP->cf_idKb, - 0, rtP->Vd_max, (int16_T)-rtP->Vd_max, &rtDW->Switch2, - &rtDW->PI_backCalc_fixdt_Id); + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt_id' */ + PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_idKp, rtP->cf_idKi, rtP->Vd_max, + (int16_T)-rtP->Vd_max, 0, &rtDW->Switch1, + &rtDW->PI_clamp_fixdt_id); - /* End of Outputs for SubSystem: '/PI_backCalc_fixdt_Id' */ + /* End of Outputs for SubSystem: '/PI_clamp_fixdt_id' */ /* End of Outputs for SubSystem: '/Vd_Calculation' */ } @@ -1751,49 +1829,44 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of If: '/If1' */ /* Abs: '/Abs5' */ - if (rtDW->Switch2 < 0) { - rtb_Switch2_d_0 = (int16_T)-rtDW->Switch2; + if (rtDW->Switch1 < 0) { + rtb_Gain4 = (int16_T)-rtDW->Switch1; } else { - rtb_Switch2_d_0 = rtDW->Switch2; + rtb_Gain4 = rtDW->Switch1; } /* End of Abs: '/Abs5' */ /* PreLookup: '/Vq_max_XA' */ - rtb_iq_max_XA = plook_u8s16_evencka(rtb_Switch2_d_0, rtP->Vq_max_XA[0], + rtb_r_fieldWeak_XA_o1 = plook_u8s16_evencka(rtb_Gain4, rtP->Vq_max_XA[0], (uint16_T)(rtP->Vq_max_XA[1] - rtP->Vq_max_XA[0]), 45U); /* Interpolation_n-D: '/Vq_max_M1' */ - rtb_Saturation2 = rtP->Vq_max_M1[rtb_iq_max_XA]; + rtb_Gain2_f = rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1]; /* Gain: '/Gain5' incorporates: * Interpolation_n-D: '/Vq_max_M1' */ - rtb_Sum6 = (int16_T)-rtP->Vq_max_M1[rtb_iq_max_XA]; + rtb_Saturation = (int16_T)-rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1]; /* PreLookup: '/iq_max_XA' */ - rtb_iq_max_XA = plook_u8s16_evencka(rtb_Saturation, rtP->iq_max_XA[0], - (uint16_T)(rtP->iq_max_XA[1] - rtP->iq_max_XA[0]), 50U); + rtb_r_fieldWeak_XA_o1 = plook_u8s16_evencka(rtb_id_fieldWeak_M1, + rtP->iq_max_XA[0], (uint16_T)(rtP->iq_max_XA[1] - rtP->iq_max_XA[0]), 50U); /* MinMax: '/MinMax' incorporates: * Constant: '/i_max' * Interpolation_n-D: '/iq_max_M1' */ - if (rtP->i_max < rtP->iq_max_M1[rtb_iq_max_XA]) { - rtb_Saturation = rtP->i_max; + if (rtP->i_max < rtP->iq_max_M1[rtb_r_fieldWeak_XA_o1]) { + rtb_id_fieldWeak_M1 = rtP->i_max; } else { - rtb_Saturation = rtP->iq_max_M1[rtb_iq_max_XA]; + rtb_id_fieldWeak_M1 = rtP->iq_max_M1[rtb_r_fieldWeak_XA_o1]; } /* End of MinMax: '/MinMax' */ /* Gain: '/Gain1' */ - rtb_Gain1 = (int16_T)-rtb_Saturation; - - /* Gain: '/Gain6' incorporates: - * Constant: '/n_max1' - */ - rtb_Gain6 = (int16_T)-rtP->n_max; + rtb_toNegative = (int16_T)-rtb_id_fieldWeak_M1; /* If: '/If1' incorporates: * Constant: '/CTRL_COMM' @@ -1823,13 +1896,13 @@ void BLDC_controller_step(RT_MODEL *const rtM) * RelationalOperator: '/UpperRelop' * Switch: '/Switch' */ - if (rtDW->Sum1[0] > rtb_Saturation) { - rtb_Switch2_d_0 = rtb_Saturation; - } else if (rtDW->Sum1[0] < rtb_Gain1) { + if (rtDW->Sum1[0] > rtb_id_fieldWeak_M1) { + rtb_Gain4 = rtb_id_fieldWeak_M1; + } else if (rtDW->Sum1[0] < rtb_toNegative) { /* Switch: '/Switch' */ - rtb_Switch2_d_0 = rtb_Gain1; + rtb_Gain4 = rtb_toNegative; } else { - rtb_Switch2_d_0 = rtDW->Sum1[0]; + rtb_Gain4 = rtDW->Sum1[0]; } /* End of Switch: '/Switch2' */ @@ -1838,17 +1911,17 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Constant: '/cf_iqKpLimProt' * Sum: '/Sum3' */ - tmp = ((int16_T)(rtb_Switch2_d_0 - rtDW->Sum1[0]) * rtP->cf_iqKpLimProt) >> + rtb_Gain3 = ((int16_T)(rtb_Gain4 - rtDW->Sum1[0]) * rtP->cf_iqKpLimProt) >> 8; - if (tmp > 32767) { - tmp = 32767; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - rtDW->Divide4 = (int16_T)tmp; + rtDW->Divide4 = (int16_T)rtb_Gain3; /* End of Product: '/Divide4' */ /* End of Outputs for SubSystem: '/Current_Limit_Protection' */ @@ -1856,6 +1929,11 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of If: '/If1' */ + /* Gain: '/Gain6' incorporates: + * Constant: '/n_max1' + */ + rtb_Gain4 = (int16_T)-rtP->n_max; + /* If: '/If2' incorporates: * Constant: '/CTRL_COMM2' * Constant: '/CTRL_COMM3' @@ -1886,12 +1964,11 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Switch: '/Switch' */ if (rtb_Switch2_fv > rtP->n_max) { - rtb_Switch2_d_0 = rtP->n_max; - } else if (rtb_Switch2_fv < rtb_Gain6) { - /* Switch: '/Switch' */ - rtb_Switch2_d_0 = rtb_Gain6; + rtb_Gain4 = rtP->n_max; } else { - rtb_Switch2_d_0 = rtb_Switch2_fv; + if (!(rtb_Switch2_fv < rtb_Gain4)) { + rtb_Gain4 = rtb_Switch2_fv; + } } /* End of Switch: '/Switch2' */ @@ -1900,17 +1977,17 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Constant: '/cf_nKpLimProt' * Sum: '/Sum1' */ - tmp = ((int16_T)(rtb_Switch2_d_0 - rtb_Switch2_fv) * rtP->cf_nKpLimProt) >> + rtb_Gain3 = ((int16_T)(rtb_Gain4 - rtb_Switch2_fv) * rtP->cf_nKpLimProt) >> 8; - if (tmp > 32767) { - tmp = 32767; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - rtDW->Divide1 = (int16_T)tmp; + rtDW->Divide1 = (int16_T)rtb_Gain3; /* End of Product: '/Divide1' */ /* End of Outputs for SubSystem: '/Speed_Limit_Protection' */ @@ -1919,14 +1996,9 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of If: '/If2' */ /* SwitchCase: '/Switch Case' incorporates: - * Constant: '/Constant23' - * Constant: '/dV_openRate' * Constant: '/cf_iqKiLimProt' - * Constant: '/cf_nKb' * Constant: '/cf_nKi' * Constant: '/cf_nKp' - * DataTypeConversion: '/Data Type Conversion' - * Gain: '/Gain3' * Product: '/Divide1' * SignalConversion: '/Signal Conversion2' * Sum: '/Sum3' @@ -1957,35 +2029,35 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ /* Sum: '/Sum3' */ - tmp = (rtb_Merge + rtDW->Divide4) + rtDW->Divide1; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = (rtb_Merge + rtDW->Divide4) + rtDW->Divide1; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' * Sum: '/Sum3' - * Switch: '/Switch' + * Switch: '/Switch' */ - if ((int16_T)tmp > rtb_Saturation2) { + if ((int16_T)rtb_Gain3 > rtb_Gain2_f) { /* SignalConversion: '/Signal Conversion2' */ - rtDW->Merge = rtb_Saturation2; - } else if ((int16_T)tmp < rtb_Sum6) { - /* Switch: '/Switch' incorporates: + rtDW->Merge = rtb_Gain2_f; + } else if ((int16_T)rtb_Gain3 < rtb_Saturation) { + /* Switch: '/Switch' incorporates: * SignalConversion: '/Signal Conversion2' */ - rtDW->Merge = rtb_Sum6; + rtDW->Merge = rtb_Saturation; } else { /* SignalConversion: '/Signal Conversion2' */ - rtDW->Merge = (int16_T)tmp; + rtDW->Merge = (int16_T)rtb_Gain3; } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch2' */ /* End of Outputs for SubSystem: '/Voltage_Mode' */ break; @@ -1995,12 +2067,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ - /* SystemReset for Atomic SubSystem: '/PI_backCalc_fixdt_n' */ + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt_n' */ /* SystemReset for SwitchCase: '/Switch Case' */ - PI_backCalc_fixdt_n_Reset(&rtDW->PI_backCalc_fixdt_n_p); + PI_clamp_fixdt_n_Reset(&rtDW->PI_clamp_fixdt_n_o); - /* End of SystemReset for SubSystem: '/PI_backCalc_fixdt_n' */ + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt_n' */ /* End of SystemReset for SubSystem: '/Speed_Mode' */ } @@ -2008,38 +2080,22 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Outputs for IfAction SubSystem: '/Speed_Mode' incorporates: * ActionPort: '/Action Port' */ - /* Switch: '/Switch2' incorporates: - * Constant: '/n_max1' - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_Merge > rtP->n_max) { - rtb_Gain6 = rtP->n_max; - } else { - if (!(rtb_Merge < rtb_Gain6)) { - rtb_Gain6 = rtb_Merge; - } - } - - /* End of Switch: '/Switch2' */ - /* Sum: '/Sum3' */ - tmp = rtb_Gain6 - rtb_Switch2_fv; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = rtb_Merge - rtb_Switch2_fv; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - /* Outputs for Atomic SubSystem: '/PI_backCalc_fixdt_n' */ - rtDW->Merge = (int16_T) PI_backCalc_fixdt_n((int16_T)tmp, rtP->cf_nKp, - rtP->cf_nKi, rtP->cf_nKb, (int16_T)((rtDW->Divide4 * rtP->cf_iqKiLimProt) - >> 10), rtb_Saturation2, rtb_Sum6, &rtDW->PI_backCalc_fixdt_n_p); + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt_n' */ + rtDW->Merge = (int16_T) PI_clamp_fixdt_n((int16_T)rtb_Gain3, rtP->cf_nKp, + rtP->cf_nKi, rtb_Gain2_f, rtb_Saturation, (int16_T)((rtDW->Divide4 * + rtP->cf_iqKiLimProt) >> 10), &rtDW->PI_clamp_fixdt_n_o); - /* End of Outputs for SubSystem: '/PI_backCalc_fixdt_n' */ + /* End of Outputs for SubSystem: '/PI_clamp_fixdt_n' */ /* End of Outputs for SubSystem: '/Speed_Mode' */ break; @@ -2050,12 +2106,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ - /* SystemReset for Atomic SubSystem: '/PI_backCalc_fixdt_Iq' */ + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt_iq' */ /* SystemReset for SwitchCase: '/Switch Case' */ - PI_backCalc_fixdt_Reset(&rtDW->PI_backCalc_fixdt_Iq); + PI_clamp_fixdt_Reset(&rtDW->PI_clamp_fixdt_iq); - /* End of SystemReset for SubSystem: '/PI_backCalc_fixdt_Iq' */ + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt_iq' */ /* End of SystemReset for SubSystem: '/Torque_Mode' */ } @@ -2064,12 +2120,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) * ActionPort: '/Action Port' */ /* Sum: '/Sum2' */ - tmp = rtb_Merge + rtDW->Divide1; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = rtb_Merge + rtDW->Divide1; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } @@ -2077,14 +2133,14 @@ void BLDC_controller_step(RT_MODEL *const rtM) * RelationalOperator: '/LowerRelop1' * Sum: '/Sum2' */ - if (!((int16_T)tmp > rtb_Saturation)) { + if (!((int16_T)rtb_Gain3 > rtb_id_fieldWeak_M1)) { /* Switch: '/Switch' incorporates: * RelationalOperator: '/UpperRelop' */ - if ((int16_T)tmp < rtb_Gain1) { - rtb_Saturation = rtb_Gain1; + if ((int16_T)rtb_Gain3 < rtb_toNegative) { + rtb_id_fieldWeak_M1 = rtb_toNegative; } else { - rtb_Saturation = (int16_T)tmp; + rtb_id_fieldWeak_M1 = (int16_T)rtb_Gain3; } /* End of Switch: '/Switch' */ @@ -2093,29 +2149,27 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of Switch: '/Switch2' */ /* Sum: '/Sum1' */ - tmp = rtb_Saturation - rtDW->Sum1[0]; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = rtb_id_fieldWeak_M1 - rtDW->Sum1[0]; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } - /* Outputs for Atomic SubSystem: '/PI_backCalc_fixdt_Iq' */ + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt_iq' */ /* SignalConversion: '/Signal Conversion2' incorporates: - * Constant: '/cf_iqKb' * Constant: '/cf_iqKi' * Constant: '/cf_iqKp' * Constant: '/constant' * Sum: '/Sum1' */ - PI_backCalc_fixdt((int16_T)tmp, rtP->cf_iqKp, rtP->cf_iqKi, rtP->cf_iqKb, - 0, rtb_Saturation2, rtb_Sum6, &rtDW->Merge, - &rtDW->PI_backCalc_fixdt_Iq); + PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_iqKp, rtP->cf_iqKi, rtb_Gain2_f, + rtb_Saturation, 0, &rtDW->Merge, &rtDW->PI_clamp_fixdt_iq); - /* End of Outputs for SubSystem: '/PI_backCalc_fixdt_Iq' */ + /* End of Outputs for SubSystem: '/PI_clamp_fixdt_iq' */ /* End of Outputs for SubSystem: '/Torque_Mode' */ break; @@ -2128,22 +2182,29 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* SystemReset for Atomic SubSystem: '/rising_edge_init' */ /* SystemReset for SwitchCase: '/Switch Case' incorporates: * UnitDelay: '/UnitDelay' + * UnitDelay: '/UnitDelay' */ rtDW->UnitDelay_DSTATE_g = true; /* End of SystemReset for SubSystem: '/rising_edge_init' */ /* SystemReset for Atomic SubSystem: '/Rate_Limiter' */ - Rate_Limiter_Reset(&rtDW->Rate_Limiter_l); + rtDW->UnitDelay_DSTATE = 0; /* End of SystemReset for SubSystem: '/Rate_Limiter' */ - /* End of SystemReset for SubSystem: '/Open_Mode' */ } /* Outputs for IfAction SubSystem: '/Open_Mode' incorporates: * ActionPort: '/Action Port' */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * UnitDelay: '/UnitDelay4' + */ + rtb_Gain3 = rtDW->UnitDelay4_DSTATE_er << 12; + rtb_DataTypeConversion = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | + -134217728 : rtb_Gain3 & 134217727; + /* Outputs for Atomic SubSystem: '/rising_edge_init' */ /* UnitDelay: '/UnitDelay' */ rtb_RelationalOperator4_d = rtDW->UnitDelay_DSTATE_g; @@ -2155,31 +2216,66 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of Outputs for SubSystem: '/rising_edge_init' */ - /* DataTypeConversion: '/Data Type Conversion' incorporates: - * UnitDelay: '/UnitDelay4' - */ - tmp = rtDW->UnitDelay4_DSTATE_er << 12; - - /* Gain: '/Gain3' incorporates: - * Constant: '/dV_openRate' - */ - tmp_3 = -rtP->dV_openRate; - /* Outputs for Atomic SubSystem: '/Rate_Limiter' */ - rtb_Sum2 = Rate_Limiter(0, (tmp & 134217728) != 0 ? tmp | -134217728 : tmp - & 134217727, rtb_RelationalOperator4_d, rtP->dV_openRate, (tmp_3 & - 134217728) != 0 ? tmp_3 | -134217728 : tmp_3 & 134217727, - &rtDW->Rate_Limiter_l); + /* Switch: '/Switch1' incorporates: + * UnitDelay: '/UnitDelay' + */ + if (rtb_RelationalOperator4_d) { + rtb_Switch1 = rtb_DataTypeConversion; + } else { + rtb_Switch1 = rtDW->UnitDelay_DSTATE; + } + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' */ + rtb_Gain3 = -rtb_Switch1; + rtb_Sum1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch2' incorporates: + * Constant: '/dV_openRate' + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Sum1 > rtP->dV_openRate) { + rtb_Sum1 = rtP->dV_openRate; + } else { + /* Gain: '/Gain3' */ + rtb_Gain3 = -rtP->dV_openRate; + rtb_Gain3 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + */ + if (rtb_Sum1 < rtb_Gain3) { + rtb_Sum1 = rtb_Gain3; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum2' */ + rtb_Gain3 = rtb_Sum1 + rtb_Switch1; + rtb_Switch1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch2' */ + if (rtb_RelationalOperator4_d) { + /* Update for UnitDelay: '/UnitDelay' */ + rtDW->UnitDelay_DSTATE = rtb_DataTypeConversion; + } else { + /* Update for UnitDelay: '/UnitDelay' */ + rtDW->UnitDelay_DSTATE = rtb_Switch1; + } + + /* End of Switch: '/Switch2' */ /* End of Outputs for SubSystem: '/Rate_Limiter' */ - /* DataTypeConversion: '/Data Type Conversion1' incorporates: - * Constant: '/Constant23' - * Constant: '/dV_openRate' - * DataTypeConversion: '/Data Type Conversion' - * Gain: '/Gain3' - */ - rtDW->Merge = (int16_T)(rtb_Sum2 >> 12); + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW->Merge = (int16_T)(rtb_Switch1 >> 12); /* End of Outputs for SubSystem: '/Open_Mode' */ break; @@ -2191,13 +2287,13 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Product: '/Divide1' * Product: '/Divide4' */ - tmp = (int16_T)((rtDW->Switch2 * rtb_Switch2_d) >> 14) - (int16_T) - ((rtDW->Merge * rtb_Add) >> 14); - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = (int16_T)((rtDW->Switch1 * rtb_Switch2_d) >> 14) - (int16_T) + ((rtDW->Merge * rtb_MinMax2) >> 14); + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } @@ -2205,33 +2301,34 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Product: '/Divide2' * Product: '/Divide3' */ - tmp_3 = (int16_T)((rtDW->Switch2 * rtb_Add) >> 14) + (int16_T)((rtDW->Merge * - rtb_Switch2_d) >> 14); - if (tmp_3 > 32767) { - tmp_3 = 32767; + rtb_DataTypeConversion = (int16_T)((rtDW->Switch1 * rtb_MinMax2) >> 14) + + (int16_T)((rtDW->Merge * rtb_Switch2_d) >> 14); + if (rtb_DataTypeConversion > 32767) { + rtb_DataTypeConversion = 32767; } else { - if (tmp_3 < -32768) { - tmp_3 = -32768; + if (rtb_DataTypeConversion < -32768) { + rtb_DataTypeConversion = -32768; } } /* Gain: '/Gain1' incorporates: * Sum: '/Sum1' */ - tmp_3 = 14189 * (int16_T)tmp_3; + rtb_DataTypeConversion = 14189 * (int16_T)rtb_DataTypeConversion; /* Sum: '/Sum6' incorporates: * Gain: '/Gain1' * Gain: '/Gain3' * Sum: '/Sum6' */ - tmp_3 = (((tmp_3 < 0 ? 16383 : 0) + tmp_3) >> 14) - ((int16_T)(((int16_T)tmp - < 0) + (int16_T)tmp) >> 1); - if (tmp_3 > 32767) { - tmp_3 = 32767; + rtb_DataTypeConversion = (((rtb_DataTypeConversion < 0 ? 16383 : 0) + + rtb_DataTypeConversion) >> 14) - ((int16_T)(((int16_T)rtb_Gain3 < 0) + + (int16_T)rtb_Gain3) >> 1); + if (rtb_DataTypeConversion > 32767) { + rtb_DataTypeConversion = 32767; } else { - if (tmp_3 < -32768) { - tmp_3 = -32768; + if (rtb_DataTypeConversion < -32768) { + rtb_DataTypeConversion = -32768; } } @@ -2239,12 +2336,12 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Sum: '/Sum6' * Sum: '/Sum6' */ - tmp_2 = -(int16_T)tmp - (int16_T)tmp_3; - if (tmp_2 > 32767) { - tmp_2 = 32767; + rtb_Switch1 = -(int16_T)rtb_Gain3 - (int16_T)rtb_DataTypeConversion; + if (rtb_Switch1 > 32767) { + rtb_Switch1 = 32767; } else { - if (tmp_2 < -32768) { - tmp_2 = -32768; + if (rtb_Switch1 < -32768) { + rtb_Switch1 = -32768; } } @@ -2253,13 +2350,13 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Sum: '/Sum6' * Sum: '/Sum6' */ - rtb_Saturation2 = (int16_T)tmp; - if (!((int16_T)tmp < (int16_T)tmp_3)) { - rtb_Saturation2 = (int16_T)tmp_3; + rtb_Switch2_d = (int16_T)rtb_Gain3; + if (!((int16_T)rtb_Gain3 < (int16_T)rtb_DataTypeConversion)) { + rtb_Switch2_d = (int16_T)rtb_DataTypeConversion; } - if (!(rtb_Saturation2 < (int16_T)tmp_2)) { - rtb_Saturation2 = (int16_T)tmp_2; + if (!(rtb_Switch2_d < (int16_T)rtb_Switch1)) { + rtb_Switch2_d = (int16_T)rtb_Switch1; } /* MinMax: '/MinMax2' incorporates: @@ -2267,83 +2364,83 @@ void BLDC_controller_step(RT_MODEL *const rtM) * Sum: '/Sum6' * Sum: '/Sum6' */ - rtb_Switch2_d = (int16_T)tmp; - if (!((int16_T)tmp > (int16_T)tmp_3)) { - rtb_Switch2_d = (int16_T)tmp_3; + rtb_Saturation = (int16_T)rtb_Gain3; + if (!((int16_T)rtb_Gain3 > (int16_T)rtb_DataTypeConversion)) { + rtb_Saturation = (int16_T)rtb_DataTypeConversion; } - if (!(rtb_Switch2_d > (int16_T)tmp_2)) { - rtb_Switch2_d = (int16_T)tmp_2; + if (!(rtb_Saturation > (int16_T)rtb_Switch1)) { + rtb_Saturation = (int16_T)rtb_Switch1; } /* Sum: '/Add' incorporates: * MinMax: '/MinMax1' * MinMax: '/MinMax2' */ - tmp_1 = rtb_Saturation2 + rtb_Switch2_d; - if (tmp_1 > 32767) { - tmp_1 = 32767; + rtb_Sum1 = rtb_Switch2_d + rtb_Saturation; + if (rtb_Sum1 > 32767) { + rtb_Sum1 = 32767; } else { - if (tmp_1 < -32768) { - tmp_1 = -32768; + if (rtb_Sum1 < -32768) { + rtb_Sum1 = -32768; } } /* Gain: '/Gain2' incorporates: * Sum: '/Add' */ - rtb_Add = (int16_T)(tmp_1 >> 1); + rtb_Gain2_f = (int16_T)(rtb_Sum1 >> 1); /* Sum: '/Add1' incorporates: * Sum: '/Sum6' */ - tmp = (int16_T)tmp - rtb_Add; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = (int16_T)rtb_Gain3 - rtb_Gain2_f; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } /* Gain: '/Gain4' incorporates: * Sum: '/Add1' */ - rtDW->Gain4[0] = (int16_T)((18919 * tmp) >> 18); + rtDW->Gain4[0] = (int16_T)((18919 * rtb_Gain3) >> 18); /* Sum: '/Add1' incorporates: * Sum: '/Sum6' */ - tmp = (int16_T)tmp_3 - rtb_Add; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = (int16_T)rtb_DataTypeConversion - rtb_Gain2_f; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } /* Gain: '/Gain4' incorporates: * Sum: '/Add1' */ - rtDW->Gain4[1] = (int16_T)((18919 * tmp) >> 18); + rtDW->Gain4[1] = (int16_T)((18919 * rtb_Gain3) >> 18); /* Sum: '/Add1' incorporates: * Sum: '/Sum2' */ - tmp = (int16_T)tmp_2 - rtb_Add; - if (tmp > 32767) { - tmp = 32767; + rtb_Gain3 = (int16_T)rtb_Switch1 - rtb_Gain2_f; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; } else { - if (tmp < -32768) { - tmp = -32768; + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; } } /* Gain: '/Gain4' incorporates: * Sum: '/Add1' */ - rtDW->Gain4[2] = (int16_T)((18919 * tmp) >> 18); + rtDW->Gain4[2] = (int16_T)((18919 * rtb_Gain3) >> 18); /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE_er = rtDW->Merge; @@ -2360,10 +2457,10 @@ void BLDC_controller_step(RT_MODEL *const rtM) * DataTypeConversion: '/Data Type Conversion8' * RelationalOperator: '/Relational Operator6' */ - if (rtP->z_ctrlTypSel == 0) { - rtb_Merge = (int16_T)(rtb_Merge >> 4); - } else { + if (rtP->z_ctrlTypSel == 1) { rtb_Merge = (int16_T)(rtDW->Merge >> 4); + } else { + rtb_Merge = (int16_T)(rtb_Merge >> 4); } /* End of Switch: '/Switch2' */ @@ -2378,9 +2475,9 @@ void BLDC_controller_step(RT_MODEL *const rtM) * 2-dimensional Direct Look-Up returning a Column */ if (rtb_LogicalOperator) { - rtb_Saturation2 = rtDW->Gain4[0]; - rtb_Switch2_d = rtDW->Gain4[1]; - rtb_Saturation = rtDW->Gain4[2]; + rtb_Switch2_d = rtDW->Gain4[0]; + rtb_Saturation = rtDW->Gain4[1]; + rtb_id_fieldWeak_M1 = rtDW->Gain4[2]; } else { if (rtConstP.vec_hallToPos_Value[rtb_Sum] > 5) { /* LookupNDDirect: '/z_commutMap_M1' @@ -2414,20 +2511,17 @@ void BLDC_controller_step(RT_MODEL *const rtM) * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ - rtb_Sum2 = rtb_Sum2_h * 3; - rtb_Saturation2 = (int16_T)(rtb_Merge * - rtConstP.z_commutMap_M1_table[rtb_Sum2]); - rtb_Switch2_d = (int16_T)(rtConstP.z_commutMap_M1_table[1 + rtb_Sum2] * - rtb_Merge); - rtb_Saturation = (int16_T)(rtConstP.z_commutMap_M1_table[2 + rtb_Sum2] * - rtb_Merge); + rtb_DataTypeConversion = rtb_Sum2_h * 3; + rtb_Switch2_d = (int16_T)(rtb_Merge * + rtConstP.z_commutMap_M1_table[rtb_DataTypeConversion]); + rtb_Saturation = (int16_T)(rtConstP.z_commutMap_M1_table[1 + + rtb_DataTypeConversion] * rtb_Merge); + rtb_id_fieldWeak_M1 = (int16_T)(rtConstP.z_commutMap_M1_table[2 + + rtb_DataTypeConversion] * rtb_Merge); } /* End of Switch: '/Switch1' */ - /* Update for UnitDelay: '/UnitDelay1' */ - rtDW->UnitDelay1_DSTATE = rtb_Sum_l; - /* Update for UnitDelay: '/UnitDelay3' incorporates: * Inport: '/b_hallA ' */ @@ -2436,7 +2530,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Update for UnitDelay: '/UnitDelay1' incorporates: * Inport: '/b_hallB' */ - rtDW->UnitDelay1_DSTATE_m = rtU->b_hallB; + rtDW->UnitDelay1_DSTATE = rtU->b_hallB; /* Update for UnitDelay: '/UnitDelay2' incorporates: * Inport: '/b_hallC' @@ -2444,7 +2538,7 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->UnitDelay2_DSTATE_f = rtU->b_hallC; /* Update for UnitDelay: '/UnitDelay3' */ - rtDW->UnitDelay3_DSTATE = rtb_Switch1_a; + rtDW->UnitDelay3_DSTATE = rtb_Switch1_l; /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE_e = rtb_Abs5; @@ -2452,16 +2546,19 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE = rtb_Merge; + /* Update for UnitDelay: '/UnitDelay1' */ + rtDW->UnitDelay1_DSTATE_p = rtb_Sum_l; + /* End of Outputs for SubSystem: '/BLDC_controller' */ /* Outport: '/DC_phaA' */ - rtY->DC_phaA = rtb_Saturation2; + rtY->DC_phaA = rtb_Switch2_d; /* Outport: '/DC_phaB' */ - rtY->DC_phaB = rtb_Switch2_d; + rtY->DC_phaB = rtb_Saturation; /* Outport: '/DC_phaC' */ - rtY->DC_phaC = rtb_Saturation; + rtY->DC_phaC = rtb_id_fieldWeak_M1; /* Outputs for Atomic SubSystem: '/BLDC_controller' */ /* Outport: '/n_mot' incorporates: @@ -2501,8 +2598,11 @@ void BLDC_controller_initialize(RT_MODEL *const rtM) rtDW->If1_ActiveSubsystem = -1; /* Start for IfAction SubSystem: '/F04_Field_Oriented_Control' */ + /* Start for If: '/If2' */ + rtDW->If2_ActiveSubsystem_a = -1; + /* Start for If: '/If1' */ - rtDW->If1_ActiveSubsystem_h = -1; + rtDW->If1_ActiveSubsystem_e = -1; /* Start for If: '/If1' */ rtDW->If1_ActiveSubsystem_f = -1; diff --git a/Src/BLDC_controller_data.c b/Src/BLDC_controller_data.c index 94b91d6..d79b74c 100644 --- a/Src/BLDC_controller_data.c +++ b/Src/BLDC_controller_data.c @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1187 + * Model version : 1.1197 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 27 17:31:20 2019 + * C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -78,7 +78,7 @@ P rtP_Left = { /* Variable: dV_openRate * Referenced by: '/dV_openRate' */ - 3932, + 4096, /* Variable: dz_cntTrnsDetHi * Referenced by: '/dz_cntTrnsDet' @@ -121,7 +121,7 @@ P rtP_Left = { 9600U, /* Variable: cf_idKp - * Referenced by: '/cf_idKp' + * Referenced by: '/cf_idKp1' */ 819U, @@ -230,40 +230,25 @@ P rtP_Left = { */ 7864U, - /* Variable: cf_idKb - * Referenced by: '/cf_idKb' - */ - 3932U, - /* Variable: cf_idKi - * Referenced by: '/cf_idKi' + * Referenced by: '/cf_idKi1' */ - 236U, - - /* Variable: cf_iqKb - * Referenced by: '/cf_iqKb' - */ - 3932U, + 246U, /* Variable: cf_iqKi * Referenced by: '/cf_iqKi' */ - 393U, + 410U, /* Variable: cf_iqKiLimProt * Referenced by: '/cf_iqKiLimProt' */ - 160U, - - /* Variable: cf_nKb - * Referenced by: '/cf_nKb' - */ - 3932U, + 167U, /* Variable: cf_nKi * Referenced by: '/cf_nKi' */ - 80U, + 84U, /* Variable: cf_iqKpLimProt * Referenced by: '/cf_iqKpLimProt' diff --git a/Src/main.c b/Src/main.c index b1f9373..94708fd 100644 --- a/Src/main.c +++ b/Src/main.c @@ -63,9 +63,6 @@ extern volatile adc_buf_t adc_buffer; extern I2C_HandleTypeDef hi2c2; extern UART_HandleTypeDef huart2; -static int cmd1; // normalized input values. -1000 to 1000 -static int cmd2; - typedef struct{ int16_t steer; int16_t speed; @@ -76,6 +73,8 @@ static volatile Serialcommand command; static uint8_t button1, button2; +static int cmd1; // normalized input value. -1000 to 1000 +static int cmd2; // normalized input value. -1000 to 1000 static int16_t steer; // local variable for steering. -1000 to 1000 static int16_t speed; // local variable for speed. -1000 to 1000 static int16_t steerFixdt; // local fixed-point variable for steering low-pass filter @@ -271,14 +270,14 @@ int main(void) { cmd1 = CLAMP(adc_buffer.l_tx2 - ADC1_MID, 0, ADC1_MAX - ADC1_MID) * 1000 / (ADC1_MAX - ADC1_MID) -CLAMP(ADC1_MID - adc_buffer.l_tx2, 0, ADC1_MID - ADC1_MIN) * 1000 / (ADC1_MID - ADC1_MIN); // ADC1 #else - cmd1 = CLAMP(adc_buffer.l_tx2 - ADC1_MIN, 0, ADC1_MAX) * 1000 / ADC1_MAX; // ADC1 + cmd1 = CLAMP(adc_buffer.l_tx2 - ADC1_MIN, 0, ADC1_MAX) * 1000 / (ADC1_MAX - ADC1_MIN); // ADC1 #endif #ifdef ADC2_MID_POT cmd2 = CLAMP(adc_buffer.l_rx2 - ADC2_MID, 0, ADC2_MAX - ADC2_MID) * 1000 / (ADC2_MAX - ADC2_MID) -CLAMP(ADC2_MID - adc_buffer.l_rx2, 0, ADC2_MID - ADC2_MIN) * 1000 / (ADC2_MID - ADC2_MIN); // ADC2 #else - cmd2 = CLAMP(adc_buffer.l_rx2 - ADC2_MIN, 0, ADC2_MAX) * 1000 / ADC2_MAX; // ADC2 + cmd2 = CLAMP(adc_buffer.l_rx2 - ADC2_MIN, 0, ADC2_MAX) * 1000 / (ADC2_MAX - ADC2_MIN); // ADC2 #endif // use ADCs as button inputs: @@ -567,7 +566,7 @@ void rateLimiter16(int16_t u, int16_t rate, int16_t *y) } } - *y = (int16_T)(q0 + *y); + *y = q0 + *y; } // =========================================================== \ No newline at end of file diff --git a/build/firmware.bin b/build/firmware.bin index 4e46d76..1072ec4 100644 Binary files a/build/firmware.bin and b/build/firmware.bin differ diff --git a/build/firmware.elf b/build/firmware.elf index 41903ec..5260199 100644 Binary files a/build/firmware.elf and b/build/firmware.elf differ diff --git a/docs/pictures/paramTable.png b/docs/pictures/paramTable.png index b7cf6d4..8606c89 100644 Binary files a/docs/pictures/paramTable.png and b/docs/pictures/paramTable.png differ